ADP1823 Datasheet, PDF (15/32 Pages) Analog Devices – Dual, Interleaved, Step-Down DC-to-DC Controller with Tracking

MOSFET DRIVERS
The DH1 and DH2 pins drive the high-side switch MOSFETs.
These are boosted 5 V gate drivers that are powered by
bootstrap capacitor circuits. This configuration allows the high-
side, n-channel MOSFET gate to be driven above the input
voltage, allowing full enhancement and a low voltage drop
across the MOSFET. The bootstrap capacitors are connected
from the SW pins to their respective BST pins. The bootstrap
Schottky diodes from the PV pins to the BST pins recharge the
bootstrap capacitors every time the SW nodes go low. Use a
bootstrap capacitor value greater than 100× the high-side
MOSFET input capacitance.
In practice, the switch node can run up to 24 V of input voltage,
and the boost nodes can operate more than 5 V above this to
allow full gate drive. The IN pin can be run from 2.9 V to 20 V.
This can provide an advantage, for example, in the case of high
frequency operation from very high input voltage. Dissipation on
the ADP1823 can be limited by running IN from a lower voltage
rail while operating the switches from the high voltage rail.
The switching cycle is initiated by the internal clock signal. The
high-side MOSFET is turned on by the DH driver, and the SW
node goes high, pulling up on the inductor. When the internally
generated ramp signal crosses the COMP pin voltage, the switch
MOSFET is turned off and the low-side synchronous rectifier
MOSFET is turned on by the DL driver. Active break-before-
make circuitry, as well as a supplemental fixed dead time, are
used to prevent cross-conduction in the switches.
The DL1 and DL2 pins provide gate drive for the low-side
MOSFET synchronous rectifiers. Internal circuitry monitors the
external MOSFETs to ensure break-before-make switching to
prevent cross-conduction. An active dead time reduction circuit
reduces the break-before-make time of the switching to limit
the losses due to current flowing through the synchronous
rectifier body diode.
The PV pin provides power to the low-side drivers. It is limited
to 5.5 V maximum input and should have a local decoupling
capacitor.
The synchronous rectifiers are turned on for a minimum time
of about 200 ns on every switching cycle in order to sense the
current. This and the nonoverlap dead times put a limit on the
maximum high-side switch duty cycle based on the selected
switching frequency. Typically, this is about 90% at 300 kHz
switching, and at 1 MHz switching, it reduces to about 70%
maximum duty cycle.
Because the two channels are 180° out of phase, if one is
operating around 50% duty cycle, it is common for it to jitter
when the other channel starts switching. The magnitude of the
ADP1823
jitter depends somewhat on layout, but it is difficult to avoid in
practice.
When the ADP1823 is disabled, the drivers shut off the external
MOSFETs, so that the SW node becomes three-stated or
changes to high impedance.
CURRENT LIMIT
The ADP1823 employs a unique, programmable, cycle-by-cycle
lossless current-limit circuit that uses a small, ordinary,
inexpensive resistor to set the threshold. Every switching cycle,
the synchronous rectifier turns on for a minimum time and the
voltage drop across the MOSFET RDSON is measured to
determine if the current is too high.
This measurement is done by an internal current-limit
comparator and an external current-limit set resistor. The
resistor is connected between the switch node (that is the drain
of the rectifier MOSFET) and the CSL pin. The CSL pin, which
is the inverting input of the comparator, forces 50 μA through
the resistor to create an offset voltage drop across it.
When the inductor current is flowing in the MOSFET rectifier,
its drain is forced below PGND by the voltage drop across its
RDSON. If the RDSON voltage drop exceeds the preset drop on the
external resistor, the inverting comparator input is similarly
forced below PGND and an overcurrent fault is flagged.
The normal transient ringing on the switch node is ignored for
100 ns after the synchronous rectifier turns on, so the overcur-
rent condition must also persist for 100 ns in order for a fault to
be flagged.
When an overcurrent event occurs, the overcurrent comparator
prevents switching cycles until the rectifier current has decayed
below the threshold. The overcurrent comparator is blanked for
the first 100 ns of the synchronous rectifier cycle to prevent
switch node ringing from falsely tripping the current limit. The
ADP1823 senses the current limit during the off cycle. When
the current-limit condition occurs, the ADP1823 resets the
internal clock until the overcurrent condition disappears. This
suppresses the start clock cycles until the overload condition is
removed. At the same time, the SS cap is discharged through a
6 kΩ resistor. The SS input is an auxiliary positive input of the
error amplifier, so it behaves like another voltage reference. The
lowest reference voltage wins. Discharging the SS voltage causes
the converter to use a lower voltage reference when switching is
allowed again. Therefore, as switching cycles continue around
the current limit, the output looks roughly like a constant
current source due to the rectifier limit, and the output voltage
droops as the load resistance decreases. When the overcurrent
condition is removed, operation resumes in soft start mode.
See the Setting the Current Limit section for more information.
Rev. A | Page 15 of 32