ADP1823 Datasheet, PDF (6/32 Pages) Analog Devices – Dual, Interleaved, Step-Down DC-to-DC Controller with Tracking

ADP1823
FUNCTIONAL BLOCK DIAGRAM
IN
VREG
LDOSD
EN1
EN2
FREQ
SYNC
COMP1
FB1
TRK1
SS1
COMP2
FB2
TRK2
UV2
SS2
0.6V
0.8V
REF
0.75V
0.55V
VREG
VREG
LINEAR REG
ADP1823
UVLO
THERMAL
SHUTDOWN
LOGIC
FAULT1 FAULT2
CK1
ILIM2
CK1
SQ
PWM
RQ
OSCILLATOR
PHASE 1 = 0°
PHASE 2 = 180°
RAMP1
CK2
RAMP2
VREG
50µA
ILIM1
–
+
+
+
0.6V
RAMP1
+
–
0.75V
+
–
0.8V
FAULT1
+
0.55V
–
–
+
+
+
0.6V
RAMP2
+
–
0.75V
+
–
CK2
SQ
PWM
PV
RQ
VREG
50µA
ILIM2
0.8V
FAULT2
+
0.55V
–
BST1
DH1
SW1
PV
DL1
PGND1
CSL1
POK1
BST2
DH2
SW2
DL2
PGND2
CSL2
POK2
GND
BOTTOM PADDLE
OF LFCSP
Figure 2. Functional Block Diagram
Rev. A | Page 6 of 32