ADP1823 Datasheet, PDF (18/32 Pages) Analog Devices – Dual, Interleaved, Step-Down DC-to-DC Controller with Tracking

ADP1823
SETTING THE CURRENT LIMIT
The current-limit comparator measures the voltage across the
low-side MOSFET to determine the load current.
The current limit is set through the current-limit resistor, RCL.
The current sense pins, CSL1 and CSL2, source 50 μA through
their respective RCL. This creates an offset voltage of RCL multiplied
by the 50 μA CSL current. When the drop across the low-side
MOSFET RDSON is equal to or greater than this offset voltage, the
ADP1823 flags a current-limit event.
Because the CSL current and the MOSFET RDSON vary over
process and temperature, the minimum current limit should be
set to ensure that the system can handle the maximum desired
load current. To do this, use the peak current in the inductor,
which is the desired current-limit level plus the ripple current,
the maximum RDSON of the MOSFET at its highest expected
temperature, and the minimum CSL current:
R_CL
=
I _LPK
R_{DSON (MAX )}
44 μA
(15)
where ILPK is the peak inductor current.
Because the buck converters are usually running fairly high
current, PCB layout and component placement may affect the
current-limit setting. An iteration of the RCL values may be
required for a particular board layout and MOSFET selection. If
alternate MOSFETs are substituted at some point in production,
the values of the RCL resistor may also need an iteration.
FEEDBACK VOLTAGE DIVIDER
The output regulation voltage is set through the feedback
voltage divider. The output voltage is reduced through the
voltage divider and drives the FB feedback input. The regulation
threshold at FB is 0.6 V. The maximum input bias current into
FB is 100 nA. For a 0.15% degradation in regulation voltage and
with 100 nA bias current, the low-side resistor, RBOT, needs to be
less than 9 kΩ, which results in 67 μA of divider current. For
RBOT, use 1 kΩ to 10 kΩ. A larger value resistor can be used, but
results in a reduction in output voltage accuracy due to the
input bias current at the FB pin, while lower values cause
increased quiescent current consumption. Choose RTOP to set
the output voltage by using the following equation:
R _TOP
=
R _BOT
⎜⎛ ^{VOUT − VFB}
⎜⎝ _VFB
⎟⎞
⎟⎠
(16)
where:
RTOP is the high-side voltage divider resistance.
RBOT is the low-side voltage divider resistance.
VOUT is the regulated output voltage.
VFB is the feedback regulation threshold, 0.6 V.
COMPENSATING THE VOLTAGE MODE BUCK
REGULATOR
Assuming the LC filter design is complete, the feedback control
system can then be compensated. Good compensation is critical
to proper operation of the regulator. Calculate the quantities in
Equation 17 through Equation 58 to derive the compensation
values. For convenience, Table 4 provides a summary of the
design equations and space for calculations. The information
can then be added to a spread-sheet for automated calculation.
The goal is to guarantee that the voltage gain of the buck
converter crosses unity at a slope that provides adequate phase
margin for stable operation. Additionally, at frequencies above
the crossover frequency, fCO, guaranteeing sufficient gain
margin and attenuation of switching noise are important
secondary goals. For initial practical designs, a good choice for
the crossover frequency is one tenth of the switching frequency,
so first calculate
f _CO
=
f _SW
10
(17)
This gives sufficient frequency range to design a compensation
that attenuates switching artifacts, while also giving sufficient
control loop bandwidth to provide good transient response.
The output LC filter is a resonant network that inflicts two poles
upon the response at a frequency fLC, so next calculate
f _LC
=
2π
1
LC
(18)
Generally speaking, the LC corner frequency is about two
orders of magnitude below the switching frequency, and
therefore about one order of magnitude below crossover. To
achieve sufficient phase margin at crossover to guarantee
stability, the design must compensate for the two poles at the
LC corner frequency with two zeros to boost the system phase
prior to crossover. The two zeros require an additional pole or
two above the crossover frequency to guarantee adequate gain
margin and attenuation of switching noise at high frequencies.
Depending on component selection, one zero might already be
generated by the equivalent series resistance (ESR) of the output
capacitor. Calculate this zero corner frequency, fESR, as
f _ESR
=
2π
1
R_ESRC_OUT
(19)
This zero is often near or below crossover and is useful in
bringing back some of the phase lost at the LC corner.
Rev. A | Page 18 of 32