AD9516-3 Datasheet, PDF (74/84 Pages) Analog Devices – 14-Output Clock Generator with Integrated 2.0 GHz VCO

AD9516-3
Reg.
Addr
(Hex) Bit(s) Name
142 <0> OUT8 Power-Down
143 <7:5> OUT9 Output Polarity
143 <4> OUT9 CMOS B
143 <3> OUT9 Select LVDS/CMOS
143 <2:1> OUT9 LVDS Output Current
143 <0> OUT9 Power-Down
Description
Power-down output (LVDS/CMOS).
<0> = 0; power on.
<0> = 1; power off.
In CMOS mode, <7:5> select the output polarity of each CMOS output.
In LVDS mode, only <5> determines LVDS polarity.
<7> <6> <5> OUT9A (CMOS) OUT9B (CMOS)
OUT9 (LVDS)
0 0 0 Noninverting Inverting
Noninverting
0 1 0 Noninverting Noninverting
Noninverting
1 0 0 Inverting
Inverting
Noninverting
1 1 0 Inverting
Noninverting
Noninverting
0 0 1 Inverting
Noninverting
Inverting
0 1 1 Inverting
Inverting
Inverting
1 0 1 Noninverting Noninverting
Inverting
1 1 1 Noninverting Inverting
Inverting
In CMOS mode, turn on/off the CMOS B output. There is no effect in LVDS mode.
<4> = 0; turn off the CMOS B output.
<4> = 1; turn on the CMOS B output.
Select LVDS or CMOS logic levels.
<3> = 0; LVDS.
<3> = 1; CMOS.
Set output current level in LVDS mode. This has no effect in CMOS mode.
<2> <1> Current (mA) Recommended Termination (Ω)
0 0 1.75
100
0 1 3.5
100
1 0 5.25
50
117
50
Power-down output (LVDS/CMOS).
<0> = 0; power on.
<0> = 1; power off.
Table 57. LVPECL Channel Dividers
Reg.
Addr
(Hex) Bit(s) Name
190 <7:4> Divider 0 Low Cycles
190 <3:0> Divider 0 High Cycles
191 <7> Divider 0 Bypass
191 <6> Divider 0 Nosync
191 <5> Divider 0 Force High
191 <4> Divider 0 Start High
191 <3:0> Divider 0 Phase Offset
Description
Number of clock cycles of the divider input during which divider output stays low.
Number of clock cycles of the divider input during which divider output stays high.
Bypass and power-down the divider; route input to divider output.
<7> = 0; use divider.
<7> = 1; bypass divider.
Nosync.
<6> = 0; obey chip-level SYNC signal.
<6> = 1; ignore chip-level SYNC signal.
Force divider output to high. This requires that nosync also be set.
<5> = 0; divider output forced to low.
<5> = 1; divider output forced to high.
Selects clock output to start high or start low.
<4> = 0; start low.
<4> = 1; start high.
Phase offset.
Rev. 0 | Page 74 of 84