AD9516-3 Datasheet, PDF (4/84 Pages) Analog Devices – 14-Output Clock Generator with Integrated 2.0 GHz VCO

AD9516-3
SPECIFICATIONS
Typical (typ) is given for VS = VS_LVPECL = 3.3 V ± 5%; VS ≤ VCP ≤ 5.25 V; TA = 25°C; RSET = 4.12 kΩ; CPRSET = 5.1 kΩ,
unless otherwise noted. Minimum (min) and maximum (max) values are given over full VS and TA (−40°C to +85°C) variation.
POWER SUPPLY REQUIREMENTS
Table 1.
Parameter
VS
VS_LVPECL
VCP
RSET Pin Resistor
CPRSET Pin Resistor
BYPASS Pin Capacitor
Min Typ Max Unit Test Conditions/Comments
3.135 3.3 3.465 V This is 3.3 V ± 5%
2.375
VS
V
This is nominally 2.5 V to 3.3 V ± 5%
VS
5.25 V This is nominally 3.3 V to 5.0 V ± 5%
4.12
kΩ Sets internal biasing currents; connect to ground
5.1
kΩ Sets internal CP current range, nominally 4.8 mA (CP_lsb = 600 μA);
actual current can be calculated by: CP_lsb = 3.06/CPRSET; connect to ground
220
nF Bypass for internal LDO regulator; necessary for LDO stability; connect to ground
PLL CHARACTERISTICS
Table 2.
Parameter
VCO (ON-CHIP)
Frequency Range
VCO Gain (KVCO)
Tuning Voltage (VT)
Frequency Pushing (Open-Loop)
Phase Noise @ 100 kHz Offset
Phase Noise @ 1 MHz Offset
REFERENCE INPUTS
Differential Mode (REFIN, REFIN)
Input Frequency
Input Sensitivity
Self-Bias Voltage, REFIN
Self-Bias Voltage, REFIN
Input Resistance, REFIN
Input Resistance, REFIN
Dual Single-Ended Mode (REF1, REF2)
Input Frequency (AC-Coupled)
Input Frequency (DC-Coupled)
Input Sensitivity (AC-Coupled)
Input Logic High
Input Logic Low
Input Current
Input Capacitance
Min Typ Max
Unit Test Conditions/Comments
1750
50
0.5
1
−108
−126
2250
VCP − 0.5
MHz
MHz/V
V
MHz/V
dBc/Hz
dBc/Hz
See Figure 15
See Figure 10
VCP ≤ VS when using internal VCO; outside of this
range, the CP spurs may increase due to CP up/
down mismatch
f = 2000 MHz
f = 2000 MHz
0
250
1.35 1.60
1.30 1.50
4.0 4.8
4.4 5.3
20
0
0.8
2.0
−100
2
250
1.75
1.60
5.9
6.4
250
250
0.8
+100
MHz
mV p-p
V
V
kΩ
kΩ
MHz
MHz
V p-p
V
V
μA
pF
Differential mode (can accommodate single-
ended input by ac grounding undriven input)
Frequencies below about 1 MHz should be
dc-coupled; be careful to match VCM (self-bias voltage)
PLL figure of merit increases with increasing
slew rate; see Figure 14
Self-bias voltage of REFIN¹
Self-bias voltage of REFIN¹
Self-biased¹
Self-biased¹
Two single-ended CMOS-compatible inputs
Slew rate > 50 V/μs
Slew rate > 50 V/μs; CMOS levels
Should not exceed VS p-p
Each pin, REFIN/REFIN (REF1/REF2)
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