AD9516-3 Datasheet, PDF (62/84 Pages) Analog Devices – 14-Output Clock Generator with Integrated 2.0 GHz VCO

AD9516-3
Reg.
Addr
(Hex) Bit(s) Name
Description
16 <5> Reset A and B Reset A and B counters (part of N divider).
Counters <5> = 0; normal.
<5> = 1; reset A and B counters.
16 <4> Reset All Reset R, A, and B counters.
Counters <4> = 0; normal.
<4> = 1; reset R, A, and B counters.
16 <3> B Counter B counter bypass. This is valid only when operating the prescaler in FD mode.
Bypass
<3> = 0; normal.
<3> = 1; B counter is set to divide-by-1. This allows the prescaler setting to determine the divide for
the N divider.
16 <2:0> Prescaler P Prescaler: DM = dual modulus and FD = fixed divide.
<2> <1> <0> Mode
Prescaler
0
0 0 FD
Divide-by-1.
0
0 1 FD
Divide-by-2.
0
1 0 DM
Divide-by-2 and divide-by-3 when A ≠ 0; divide-by-2 when A = 0.
0
1 1 DM
Divide-by-4 and divide-by-5 when A ≠ 0; divide-by-4 when A = 0.
1
0 0 DM
Divide-by-8 and divide-by-9 when A ≠ 0; divide-by-8 when A = 0.
1
0 1 DM
Divide-by-16 and divide-by-17 when A ≠ 0; divide-by-16 when A = 0.
1
1 0 DM
Divide-by-32 and divide-by-33 when A ≠ 0; divide-by-32 when A = 0.
1
1 1 FD
Divide-by-3.
17 <7:2> STATUS
Select the signal that is connected to the STATUS pin
Pin Control
<7> <6> <5> <4> <3>
Level or
Dynamic
<2> Signal
Signal at STATUS Pin
0
000 0
0 LVL
Ground (dc).
0
000 0
1 DYN
N divider output (after the delay).
0
000 1
0 DYN
R divider output (after the delay).
0
000 1
1 DYN
A divider output.
0
001 0
0 DYN
Prescaler output.
0
001 0
1 DYN
PFD up pulse.
0
001 1
0 DYN
PFD down pulse.
0
XXX X
X LVL
Ground (dc); for all other cases of 0XXXXX not specified above.
The selections that follow are the same as REFMON.
1
000 0
0 LVL
Ground (dc).
1
000 0
1 DYN
REF1 clock (differential reference when in differential mode).
1
000 1
0 DYN
REF2 clock (N/A in differential mode).
1
000 1
1 DYN
Selected reference to PLL (differential reference when in
differential mode).
1
001 0
0 DYN
Unselected reference to PLL (not available in differential
mode).
1
001 0
1 LVL
Status of selected reference (status of differential reference);
active high.
1
001 1
0 LVL
Status of unselected reference (not available in differential
mode); active high.
1
001 1
1 LVL
Status REF1 frequency (active high).
1
010 0
0 LVL
Status REF2 frequency (active high).
1
010 0
1 LVL
(Status REF1 frequency) AND (status REF2 frequency).
1
010 1
0 LVL
(DLD) AND (status of selected reference) AND (status of VCO).
1
010 1
1 LVL
Status of VCO frequency (active high).
1
011 0
0 LVL
Selected reference (low = REF1, high = REF2).
1
011 0
1 LVL
Digital lock detect (DLD); active high.
1
011 1
0 LVL
Holdover active (active high).
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