AD9516-3 Datasheet, PDF (1/84 Pages) Analog Devices – 14-Output Clock Generator with Integrated 2.0 GHz VCO

14-Output Clock Generator with
Integrated 2.0 GHz VCO
AD9516-3
FEATURES
Low phase noise, phase-locked loop
On-chip VCO tunes from 1.75 GHz to 2.25 GHz
External VCO/VCXO to 2.4 GHz optional
1 differential or 2 single-ended reference inputs
Reference monitoring capability
Auto and manual reference switchover/holdover modes
Autorecover from holdover
Accepts references to 250 MHz
Programmable delays in path to PFD
Digital or analog lock detect, selectable
3 pairs of 1.6 GHz LVPECL outputs
Each pair shares 1 to 32 dividers with coarse phase delay
Additive output jitter 225 fS rms
Channel-to-channel skew paired outputs <10 ps
2 pairs of 800 MHz LVDS clock outputs
Each pair shares two cascaded 1 to 32 dividers with coarse
phase delay
Additive output jitter 275 fS rms
Fine delay adjust (ΔT) on each LVDS output
Eight 250 MHz CMOS outputs (two per LVDS output)
Automatic synchronization of all outputs on power-up
Manual synchronization of outputs as needed
Serial control port
64-lead LFCSP
APPLICATIONS
Low jitter, low phase noise clock distribution
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
High performance instrumentation
Broadband infrastructure
ATE
GENERAL DESCRIPTION
The AD9516-3¹ provides a multi-output clock distribution
function with subpicosecond jitter performance, along with an on-
chip PLL and VCO. The on-chip VCO tunes from 1.75 GHz to
2.25 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz
may be used.
The AD9516-3 emphasizes low jitter and phase noise to
maximize data converter performance, and it can benefit other
applications with demanding phase noise and jitter requirements.
FUNCTIONAL BLOCK DIAGRAM
CP
LF
REFIN
REF1
REF2
STATUS
MONITOR
VCO
CLK
DIVIDER
AND MUXs
DIV/Φ
LVPECL
DIV/Φ
LVPECL
DIV/Φ
DIV/Φ
DIV/Φ
DIV/Φ
DIV/Φ
LVPECL
ΔT
LVDS/CMOS
ΔT
ΔT
LVDS/CMOS
ΔT
SERIAL CONTROL PORT
AND
DIGITAL LOGIC
AD9516-3
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
Figure 1.
The AD9516-3 features six LVPECL outputs (in three pairs);
four LVDS outputs (in two pairs); and eight CMOS outputs
(two per LVDS output). The LVPECL outputs operate to 1.6 GHz,
the LVDS outputs operate to 800 MHz, and the CMOS outputs
operate to 250 MHz.
Each pair of outputs has dividers that allow both the divide
ratio and coarse delay (or phase) to be set. The range of division
for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs
allow a range of divisions up to a maximum of 1024.
The AD9516-3 is available in a 64-lead LFCSP and can be
operated from a single 3.3 V supply. An external VCO, which
requires an extended voltage range, can be accommodated
by connecting the charge pump supply (VCP) to 5.5 V. A
separate LVPECL power supply can be from 2.375 V to 3.6 V.
The AD9516-3 is specified for operation over the standard
industrial range of −40°C to +85°C.
1 _{AD9516 is used throughout to refer to all the members of the AD9516}
family. However, when AD9516-3 is used, it is referring to that specific
member of the AD9516 family.
Rev. 0
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