AD9516-3 Datasheet, PDF (46/84 Pages) Analog Devices – 14-Output Clock Generator with Integrated 2.0 GHz VCO

AD9516-3
Table 43. Divider 3 and Divider 4 Duty Cycle; VCO Divider
Used; Duty Cycle Correction On (DCCOFF = 0); VCO
Divider Input Duty Cycle = X%
VCO
Divider
Even
Odd = 3
Odd = 5
Even
Odd
Even
Odd = 3
Odd = 5
Even
Odd
Even
Odd
Even
Odd = 3
Odd = 5
DX.1
NX.1 + MX.1 + 2
1
1
1
Even
(NX.1 = MX.1)
Even
(NX.1 = MX.1)
Odd
(MX.1 = NX.1 + 1)
Odd
(MX.1 = NX.1 + 1)
Odd
(MX.1 = NX.1 + 1)
Even
(NX.1 = MX.1)
Even
(NX.1 = MX.1)
Odd
(MX.1 = NX.1 + 1)
Odd
(MX.1 = NX.1 + 1)
Odd
(MX.1 = NX.1 + 1)
Odd
(MX.1 = NX.1 + 1)
Odd
(MX.1 = NX.1 + 1)
DX.2
NX.2 + MX.2 + 2
1
1
1
1
1
1
1
1
Even
(NX.2 = MX.2)
Even
(NX.2 = MX.2)
Even
(NX.2 = MX.2)
Even
(NX.2 = MX.2)
Odd
(MX.2 = NX.2 + 1)
Odd
(MX.2 = NX.2 + 1)
Odd
(MX.2 = NX.2 + 1)
Output
Duty Cycle
50%
(1 + X%)/3
(2 + X%)/5
50%
50%
50%
(3NX.1 + 4 + X%)/
(6NX.1 + 9)
(5NX.1 + 7 + X%)/
(10NX.1 + 15)
50%
50%
50%
50%
50%
(6NX.1NX.2 + 9NX.1 +
9NX.2 + 13 + X%)/
(3(2NX.1 + 3)
(2NX.2 + 3))
(10NX.1NX.2 + 15NX.1 +
15NX.2 + 22 + X%)/
(5(2 NX.1 + 3)
(2 NX.2 + 3))
Table 44. Divider 3 and Divider 4 Duty Cycle; VCO Divider
Not Used; Duty Cycle Correction On (DCCOFF = 0)
Input
Clock
Duty
Cycle
DX.1
NX.1 + MX.1 + 2
DX.2
NX.2 + MX.2 + 2
Output
Duty Cycle
50% 1
1
50%
50% Even
1
(NX.1 = MX.1)
50%
X% 1
1
X% (High)
X% Even
1
(NX.1 = MX.1)
50%
50%
Odd
1
(MX.1 = NX.1 + 1)
50%
X% Odd
1
(MX.1 = NX.1 + 1)
(NX.1 + 1 + X%)/
(2NX.1 + 3)
Odd
1
(MX.1 = NX.1 + 1)
(NX.1 + 1 + X%)/
(2NX.1 + 3)
50%
Even
(NX.1 = MX.1)
Even
(NX.2 = MX.2)
50%
X% Even
(NX.1 = MX.1)
Even
(NX.2 = MX.2)
50%
50%
Odd
Even
(MX.1 = NX.1 + 1) (NX.2 = MX.2)
50%
X% Odd
Even
(MX.1 = NX.1 + 1) (NX.2 = MX.2)
50%
50%
Odd
Odd
50%
(MX.1 = NX.1 + 1) (MX.2 = NX.2 + 1)
X% Odd
Odd
(2NX.1NX.2 + 3NX.1 +
(MX.1 = NX.1 + 1) (MX.2 = NX.2 + 1) 3NX.2 + 4 + X%)/
((2NX.1 + 3)(2NX.2 + 3))
Phase Offset or Coarse Time Delay (Divider 3 and Divider 4)
Divider 3 and Divider 4 can be set to have a phase offset or
delay. The phase offset is set by a combination of the bits in the
phase offset and start high registers (see Table 45).
Table 45. Setting Phase Offset and Division for Divider 3 and
Divider 4
Start
Phase
Low
Divider High (SH) Offset (PO) Cycles M
High
Cycles N
3 3.1 0x19C<0> 0x19A<3:0> 0x199<7:4> 0x199<3:0>
3.2 0x19C<1> 0x19A<7:4> 0x19B<7:4> 0x19B<3:0>
4 4.1 0x1A1<0> 0x19F<3:0> 0x19E<7:4> 0x19E<3:0>
4.2 0x1A1<1> 0x19F<7:4> 0x1A0<7:4> 0x1A0<3:0>
Let:
Δt = delay (in seconds).
Φx.y = 16 × SH<0> + 8 × PO<3> + 4 × PO<2> + 2 × PO<1> +
1 × PO<0>.
TX.1 = period of the clock signal at the input to DX.1 (in seconds).
TX.2 = period of the clock signal at the input to DX.2 (in seconds).
Rev. 0 | Page 46 of 84