EVAL-AD7741-42EBZ Datasheet, PDF(7/12 Page) Analog Devices – Single and Multichannel, Synchronous Voltage-to-Frequency Converters

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EVAL-AD7741-42EBZ Datasheet, PDF (7/12 Pages) Analog Devices – Single and Multichannel, Synchronous Voltage-to-Frequency Converters

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AD7741/AD7742

TERMINOLOGY

INTEGRAL NONLINEARITY

For the VFC, Integral Nonlinearity (INL) is a measure of the

maximum deviation from a straight line passing through the

actual endpoints of the VFC transfer function. The error is

expressed in % of the frequency span:

Frequency Span = fOUT(max) â fOUT(min)

OFFSET ERROR

This is a measure of the offset error of the VFC. Ideally, the

minimum output frequency (corresponding to minimum input

voltage) is 5% of fCLKIN The deviation from this value is the

offset error. It is expressed in terms of the error referred to the

input voltage. It is expressed in mV.

GAIN ERROR

This is a measure of the span error of the VFC. The gain is the

scale factor that relates the input VIN to the output fOUT. The

gain error is the deviation in slope of the actual VFC transfer

characteristic from the ideal expressed as a percentage of the

full-scale span.

OFFSET ERROR DRIFT

This is a measure of the change in Offset Error with changes in

temperature. It is expressed in ÂµV/Â°C.

GAIN ERROR DRIFT

This is a measure of the change in Gain Error with changes in

temperature. It is expressed in (ppm of span)/Â°C.

POWER-SUPPLY REJECTION RATIO (PSRR)

This indicates how the output of the VFC is affected by changes

in the supply voltage. Again, this error is referred to the input

voltage. The input voltage is kept constant and the VDD supply

is varied Â± 5%. The ratio of the apparent change in input voltage

to the change in VDD is measured in dBs.

CHANNEL-TO-CHANNEL ISOLATION

This is a ratio of the amplitude of the signal at the input of one

channel to a sine wave on the input of another channel. It is

measured in dBs.

COMMON-MODE REJECTION

For the AD7742, the output frequency should remain un-

changed provided the differential input remains unchanged

although its common-mode level may change. The CMR is the

ratio of the apparent change in differential input voltage to the

actual change in common-mode voltage. It is expressed in dBs.

GENERAL DESCRIPTION

The AD7741/AD7742 are a new generation of CMOS synchro-

nous Voltage-to-Frequency Converters (VFCs) that use a

charge-balance conversion technique. The AD7741 is a single-

channel version and the AD7742 is a multichannel version. The

input voltage signal is applied to a proprietary programmable

gain front-end based around an analog modulator that converts

the input voltage into an output pulse train.

The parts also contain an on-chip +2.5 V bandgap reference

and operate from a single +5 V supply. A block diagram of the

AD7742 is shown in Figure 2.

VIN1

VIN2

VIN3

VIN4

INPUT

MUX

SWITCHED

CAPS

INTEGRATOR

SWITCHED

CAPS

COMPARATOR

fOUT

Figure 2. AD7742 Block Diagram

Input Amplifier Stage

The buffered input stage for the analog inputs presents a high

impedance, allowing significant external source impedances.

The four analog inputs (VIN1 through VIN4) each have a voltage

range from +0.5 V to VDD â 1.75 V. This is an absolute voltage

range and is relative to the GND pin.

In the case of the AD7742 multichannel part, a differential

multiplexer switches one of the differential input channels to the

VFC modulator. The multiplexer is controlled by two pins, A1

and A0. See Table I for channel configurations.

Table I. AD7742 Input Channel Selection

A1 A0

VIN(+)

VIN1

VIN2

VIN3

VIN1

VIN(â)

VIN4

VIN2

Type

Pseudo Differential

Full Differential

Analog Input Ranges

The AD7741 has a unipolar single-ended input channel whereas

the AD7742 contains four input channels which may be con-

figured as two fully differential channels or as three pseudo-

differential channels. The AD7742 also has a X1/X2 gain

option on the front end. The channel and gain settings are

pin-programmable.

The AD7742 uses differential inputs to provide common-mode

noise rejection (i.e., the converted result will correspond to the

differential voltage between the two inputs). The absolute voltage

on both inputs must lie between +0.5 V and VDD â1.75 V.

REV. 0

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