EVAL-AD7741-42EBZ Datasheet, PDF (6/12 Pages) Analog Devices – Single and Multichannel, Synchronous Voltage-to-Frequency Converters

AD7741/AD7742
Pin No.
1
2
Mnemonic
f_OUT
V_DD
3
GND
4–5
A1, A0
6
CLKOUT
7
CLKIN
8
UNI/BIP
9
REFOUT
10
REFIN
11
V_IN1
12
V_IN2
13
V_IN3
14
V_IN4
15
GAIN
16
PD
AD7742 PIN FUNCTION DESCRIPTION
Function
Frequency Output. This pin provides the output of the synchronous VFC.
Power Supply Input. These parts can be operated from +4.75 V to +5.25 V and the supply should be
adequately decoupled to GND.
Ground reference point for all circuitry on the part.
Address Inputs used to select the input channel configuration.
External Clock Output. When the master clock for the device is a crystal, the crystal is connected be-
tween CLKIN and CLKOUT. When an external clock is applied to CLKIN, the CLKOUT pin
provides an inverted clock signal. This clock should be buffered if it is to be used as a clock source
elsewhere in the system.
External Clock Input. The master clock for the device can be provided in the form of a crystal or an
external clock. A crystal may be tied across the CLKIN and CLKOUT pins. Alternatively, the CLKIN
pin may be driven by a CMOS-compatible clock and CLKOUT left unconnected. The frequency of the
master clock may be as high as 6 MHz.
Control input which determines whether the device operates with differential bipolar analog input
signals or differential unipolar analog input signals.
2.5 V Voltage Reference Output. This can be tied directly to REFIN. It may also be used as a reference
to other parts of the system provided it is buffered first.
This is the Reference Input to the core of the VFC and defines the span of the VFC. A 2.5 V reference
is required at this pin. This may be provided by connecting it directly to REFOUT or by using a preci-
sion external reference (e.g., REF192).
Buffered Analog Input Channel 1. This is either a pseudo-differential input with respect to V_IN4 or it is
the positive input of a truly-differential input pair with respect to V_IN2.
Buffered Analog Input Channel 2. This is either a pseudo-differential input with respect to V_IN4 or it is
the negative input of a truly-differential input pair with respect to V_IN1.
Buffered Analog Input Channel 3. This is the positive input of a truly-differential input pair with re-
spect to V_IN4.
Buffered Analog Input Channel 4. This is either the common for pseudo-differential input with respect
to V_IN1 or V_IN2 or it is the negative input of a truly-differential input pair with respect to V_IN3.
Gain Select input that controls whether the gain on the analog front-end is X1 or X2.
Active Low Power-Down pin. When this input is low, the part enters power-down mode where it typi-
cally consumes 25 µA of current.
PIN CONFIGURATION
f_OUT 1
16 PD
V_DD 2
15 GAIN
GND 3
14 V_IN4
A1 4 AD7742 13 V_IN3
TOP VIEW
A0 5 _{(Not to Scale)} 12 V_IN2
CLKOUT 6
11 V_IN1
CLKIN 7
10 REFIN
UNI/BIP 8
9 REFOUT
–6–
REV. 0