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EVAL-AD7741-42EBZ Datasheet, PDF (3/12 Pages) Analog Devices – Single and Multichannel, Synchronous Voltage-to-Frequency Converters
AD7741/AD7742
AD7742–SPECIFICATIONS (VDD = +4.75 V to +5.25 V; VREF = +2.5 V; fCLKIN = 6.144 MHz; all specifications TMIN to
TMAX unless otherwise noted.)
Parameter3
B Version1
Min
Typ
Max
Y Version2
Min
Typ
Max
Units
Conditions/Comments
DC PERFORMANCE
Integral Nonlinearity
fCLKIN = 200 kHz4
fCLKIN = 3 MHz4
fCLKIN = 6.144 MHz
Offset Error
Gain Error
Offset Error Drift4
Gain Error Drift4
Power Supply Rejection Ratio4
Channel-to-Channel Isolation4
Common-Mode Rejection
ANALOG INPUTS (VIN1–VIN4)6
Input Current
Common-Mode Input Range
Differential Input Range
VOLTAGE REFERENCE
REFIN
Nominal Input Voltage
Input Impedance4
fCLKIN = 3 MHz
fCLKIN = 6.144 MHz
REFOUT
Output Voltage
Output Impedance4
Reference Drift4
Line Rejection
Reference Noise
(0.1 Hz to 10 Hz)4
+0.2
+1.2
+0.2
+1.2
± 12
± 12
±2
±4
–70
–75
–60
–78
± 50
+0.5
–VREF/Gain
0
2.5
70
35
2.38
2.50
1
± 50
–70
100
± 0.0122
± 0.0122
± 0.0122
± 40
± 40
+2.2
+0.2
+1.2
+2.2
+0.2
+1.2
± 12
± 12
±2
±4
–70
–75
–58
–78
± 100
± 50
VDD – 1.75 +0.5
+VREF/Gain –VREF/Gain
+VREF/Gain 0
2.5
70
35
2.60
2.38
2.50
1
± 50
–70
100
± 0.015
± 0.015
± 0.015
± 40
± 40
+2.2
+2.2
% of Span5
% of Span
% of Span
mV
mV
% of Span
% of Span
µV/°C
µV/°C
ppm of Span/°C
ppm of Span/°C
dB
dB
dB
Unipolar Mode
Bipolar Mode
Unipolar Mode
Bipolar Mode
Unipolar Mode
Bipolar Mode
Unipolar Mode
Bipolar Mode
∆VDD = ± 5%
± 100
nA
VDD – 1.75 V
+VREF/Gain V
+VREF/Gain V
Bipolar Mode
Unipolar Mode
V
kΩ
kΩ
2.60
V
kΩ
ppm/°C
dB
µV p-p
LOGIC OUTPUT
Output High Voltage, VOH
4.0
4.0
V
Output Low Voltage, VOL
0.4
0.4
V
Minimum Output Frequency
0.05 fCLKIN
0.05 fCLKIN
Hz
Maximum Output Frequency
0.45 fCLKIN
0.45 fCLKIN
Hz
Output Sourcing 800 µA7
Output Sinking 1.6 mA7
VIN = 0 V (Unipolar), VIN =
–VREF/Gain (Bipolar)
VIN = VREF/Gain (Unipolar
and Bipolar)
LOGIC INPUT
ALL EXCEPT CLKIN
Input High Voltage, VIH
2.4
Input Low Voltage, VIL
Input Current
Pin Capacitance
6
CLKIN ONLY
Input High Voltage, VIH
3.5
Input Low Voltage, VIL
Input Current
Pin Capacitance
6
2.4
0.8
± 100
10
6
3.5
0.8
±2
10
6
V
0.8
V
± 100
nA
10
pF
V
0.8
V
±2
µA
10
pF
CLOCK FREQUENCY
Input Frequency
6.144
6.144
MHz
For Specified Performance
POWER REQUIREMENTS
VDD
IDD (Normal Mode)
IDD (Power-Down)
Power-Up Time4
4.75
5.25
4.75
5.25
V
6
8
6
8
mA
25
35
25
35
µA
30
30
µs
Output Unloaded
Coming Out of Power-
Down Mode
NOTES
1Temperature range: B Version: –40°C to +85°C.
2Temperature range: Y Version: –40°C to +105°C.
3See Terminology.
4Guaranteed by design and characterization, not production tested.
5Span = Maximum Output Frequency–Minimum Output Frequency.
6The absolute voltage on the input pins must not go more positive than VDD – 1.75 V or more negative than +0.5 V.
7These logic levels apply to CLKOUT only when it is loaded with one CMOS load.
Specifications subject to change without notice.
REV. 0
–3–