ADATE305 Datasheet, PDF(52/56 Page) Analog Devices – 250 MHz Dual Integrated DCL with Level Setting DACs, Per Pin PMU, and Per Chip VHH

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ADATE305 Datasheet, PDF (52/56 Pages) Analog Devices – 250 MHz Dual Integrated DCL with Level Setting DACs, Per Pin PMU, and Per Chip VHH

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ADATE305

6.5V 1

OVD HIGH LEVEL

DAC (ADDR[4:0] = 0x0A, CH[1])

DUT

â2.5V 1

OVD LOW LEVEL

DAC (ADDR[4:0] = 0x0A, CH[0])

(ADDR[4:0] = 0x12) DATA[0]

OVD MASK ENABLES OVD

FLAGS TO ALARM OVD_CHx PIN

OVD_CHx

SHORT-CIRCUIT

CURRENT = 100ÂµA

ADATE305

PMU

V/I CLAMP

FLAG

(ADDR[4:0] = 0x12) DATA[1]

PMU MASK ENABLES PMU V/I

FLAG TO ALARM OVD_CHx PIN

(ADDR[4:0] = 0x13) 2 DATA[2] DATA[1] DATA[0]

1THE OVD HIGH/LOW LEVEL DAC IS SHARED BY EACH CHANNEL; THEREFORE, ONLY ONE OVD HIGH/LOW VOLTAGE

LEVEL CAN BE SET PER CHIP. THE OVD DACs PROVIDE A VOLTAGE RANGE OF â3V TO +7V. THE RECOMMENDED

HIGH/LOW SETTINGS ARE +6.5V/â2.5V. (THESE VALUES NEED TO BE PROGRAMMED BY THE USER UPON STARTUP/RESET.)

2THIS IS A READ ONLY REGISTER THAT ALLOWS THE USER TO DETERMINE THE CAUSE OF THE ACTIVE OVD FLAG.

Figure 84. OVD Block Diagram

Rev. 0 | Page 52 of 56

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