ADATE305 Datasheet, PDF (50/56 Pages) Analog Devices – 250 MHz Dual Integrated DCL with Level Setting DACs, Per Pin PMU, and Per Chip VHH

ADATE305
DUT0
VOH0
VOL0
VOH0
DDUU TT00––
DUT1 DDUU TT11
DIFFERENTIAL
BUFFER
VOL0
–
VOH
+NWC
+VOL
–NWC
–
VOH
DMC
+
+
VOL
–DMC
2:1 ^COMP_QH0
MUX
DIFFERENTIAL
COMPARATOR ENABLE
DATA[0] (ADDR[4:0] = 0x10)
2:1 COMP_QL0
MUX
NOTES
1. DIFFERENTIAL COMPARATOR ONLY ON CHANNEL 0.
Figure 81. Comparator Block Diagram
RECEIVER
100Ω
OUT HIGH = 1.55V
OUT CM = 1.42V
OUT LOW = 1.30V
COMPARATOR
OUTPUT (AB)
VTT = 3.3V
50Ω
50Ω
GND
Figure 82. Comparator Output Scheme
Rev. 0 | Page 50 of 56