ADATE305 Datasheet, PDF (37/56 Pages) Analog Devices – 250 MHz Dual Integrated DCL with Level Setting DACs, Per Pin PMU, and Per Chip VHH

READ OPERATION
The read operation is a two-stage operation. First, a word is
shifted in, specifying which register to read. CS is deasserted
for three clock cycles, and then a second word is shifted in to
obtain the readback data. This second word can be either
another operation or an NOP address. If another operation is
shifted in, it needs to shift in at least eight bits of data to read
ADATE305
back the previous specified data. The NOP address can be used
for this read if there is no need to write/read another register. To
maintain the clarity of the operation, it is strongly recommended
that the NOP address be used for all reads.
Any register read that is fewer than 16 bits has zeroes filled in
the top bits to make it a 16-bit word.
CS
INPUT
SCLK
INPUT
SDIN
INPUT
SDOUT
OUTPUT
NOTES
1. X = DON’T CARE.
READ INSTRUCTION
X
X
NOP
READ DATA
Figure 75. SPI Read Overview
X
X
CS
INPUT
SCLK
INPUT
SDIN
INPUT
SDOUT
OUTPUT
DATA[15:0], VALUE IS A DON’T CARE
CH[1] CH[0]
R/W ADDR[4] ADDR[3] ADDR[2] ADDR[1] ADDR[0]
X
0
1
2
13
14
15
16
17
18
19
20
21
22
23
24
25
X
NOTES
1. X = DON’T CARE.
Figure 76. SPI Read—Details of Read Request
CS
INPUT
SCLK
INPUT
SDIN
INPUT
SDOUT
OUTPUT
DATA[15:0], VALUE IS A DON’T CARE
CH[1] CH[0] R/W = 1
ADDR[4:0] = 0x00 (NOP)
X
0
1
2
13
14
15
16
17
18
19
20
21
22
23
24
25
RDATA[15] RDATA[14]
RDATA[2] RDATA[1] RDATA[0]
X
NOTES
1. RDATA IS THE REGISTER VALUE BEING READ.
2. X = DON’T CARE.
Figure 77. SPI Read—Details of Read Out
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