ADATE305 Datasheet, PDF (4/56 Pages) Analog Devices – 250 MHz Dual Integrated DCL with Level Setting DACs, Per Pin PMU, and Per Chip VHH

ADATE305
SPECIFICATIONS
Characterization and production tests performed using Power Supply Range 1 (see Table 36). VDD = +10.0 V, VCC = +3.3 V, VSS = −5.25 V,
VPLUS = +16.75 V, VCOMP_VTT = +3.3 V, VREF = +5.0 V, VREF_GND = 0.0 V. All default test conditions are as defined in Table 38. All specified
values are at TJ = 70°C, where TJ corresponds to the internal temperature sensor, unless otherwise noted. Temperature coefficients are
measured at TJ = 70°C ± 20°C, unless otherwise noted. Typical values are based on design, simulation analyses, and/or limited bench
evaluations. Typical values are not tested or guaranteed. Test levels are specified in the Explanation of Test Levels section.
TOTAL FUNCTION
Table 1.
Parameter
TOTAL FUNCTION
Output Leakage Current
PE Disable Range E
PE Disable Range A, B, C, D
High-Z Mode
Output Capacitance
DUT Pin Range
POWER SUPPLIES
Total Supply Range, VPLUS to VSS
VPLUS Supply, VPLUS
Positive Supply, VDD
Negative Supply, VSS
Logic Supply, VCC
Comparator Termination, VCOMP_VTT
VPLUS Supply Current, IPLUS
VPLUS Supply Current, IPLUS
Logic Supply Current, ICC
Comparator Termination Current,
ICOMP_VTT
Positive Supply Current, IDD
Negative Supply Current, ISS
Total Power Dissipation
Positive Supply Current, IDD
Negative Supply Current, ISS
Total Power Dissipation
TEMPERATURE MONITORS
Temperature Sensor Gain
Temperature Sensor Accuracy
Without Calibration over
25°C to 100°C
VREF INPUT
Reference Input Voltage Range for
DACs (VREF Pin)
Input Bias Current
Test
Min Typ Max Unit Level Conditions/Comments
−20.0 5.3 +20.0 nA P
5.3
nA
CT
−400 5.4 +400 nA P
4
−1.5
pF S
+6.0 V
D
22.5 23.25 V
D
16.25 16.75 17.25 V
D
9.5 10.0 10.5 V
D
−5.50 −5.25 −5.00 V
D
3.1 3.3 3.5 V
D
3.3
5.0 V
D
−1.0 +1.3 +3.0 mA P
4.0 12.7 17.0 mA P
1.0 2.7 10.0 mA P
10.0 17 26.0 mA P
72 92 105 mA P
100 119 135 mA P
1.0 1.7 1.9 W
P
102 133 154 mA P
130 158 183 mA P
1.8 2.2 2.5 W
P
10
mV/K CT
6
°C
CT
−1.5 V < VDUTx < +6.0 V; PMU and PE disabled via SPI; PMU
Range E, VCH = 7.0 V, VCL = −2.5 V
−1.5 V < VDUTx < +6.0 V; PMU and PE disabled via SPI; PMU
Range A, PMU Range B, PMU Range C, and PMU Range D,
VCH = +7.0 V, VCL = −2.5 V
−1.5 V < VDUTx < +6.0 V; PMU disabled and PE enabled via SPI;
RCV active, VCH = +7.0 V, VCL = −2.5 V
VTERM mode operation
Defines PSRR conditions
Defines PSRR conditions
Defines PSRR conditions
Defines PSRR conditions
Defines PSRR conditions
HVOUT disabled
HVOUT enabled, RCV active, no load, VHH = 12 V
Quiescent (SPI is static)
Load power down (IOH = IOL = 0 mA)
Load power down (IOH = IOL = 0 mA)
Load power down (IOH = IOL = 0 mA)
Load active off (IOH = IOL = 12 mA)
Load active off (IOH = IOL = 12 mA)
Load active off (IOH = IOL = 12 mA)
Temperature voltage available on Pin 3 at all times and Pin 28
when selected (see Table 24 and Table 36)
4.95 5
5.05 V
D
0.1 100 μA P
Referenced to VREF_GND; not referenced to VDUTGND
Tested with 5 V applied
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