EVAL-AD1835AEB Datasheet, PDF (4/24 Pages) Analog Devices – 2 ADC, 8 DAC, 96 kHz, 24-Bit Codecs

AD1835A
TIMING SPECIFICATIONS
Parameter
MASTER CLOCK AND RESET
t_MH
MCLK High
t_ML
MCLK Low
t_PDR
PD/RST Low
SPI^® PORT
t_CCH
t_CCL
t_CCP
t_CDS
t_CDH
t_CLS
t_CLH
t_COE
t_COD
t_COTS
CCLK High
CCLK Low
CCLK Period
CDATA Setup
CDATA Hold
CLATCH Setup
CLATCH Hold
COUT Enable
COUT Delay
COUT Three-State
DAC SERIAL PORT (48 kHz and 96 kHz)
Normal Mode (Slave)
t_DBH
DBCLK High
t_DBL
DBCLK Low
f_DB
DBCLK Frequency
t_DLS
DLRCLK Setup
t_DLH
DLRCLK Hold
t_DDS
DSDATA Setup
t_DDH
DSDATA Hold
Packed 128/256 Modes (Slave)
t_DBH
t_DBL
f_DB
t_DLS
t_DLH
t_DDS
t_DDH
DBCLK High
DBCLK Low
DBCLK Frequency
DLRCLK Setup
DLRCLK Hold
DSDATA Setup
DSDATA Delay
ADC SERIAL PORT (48 kHz and 96 kHz)
Normal Mode (Master)
t_ABD
ABCLK Delay
t_ALD
ALRCLK Delay Low
t_ABDD
ASDATA Delay
Normal Mode (Slave)
t_ABH
ABCLK High
t_ABL
ABCLK Low
f_AB
ABCLK Frequency
t_ALS
ALRCLK Setup
t_ALH
ALRCLK Hold
t_ABDD
ASDATA Delay
Packed 128/256 Mode (Master)
t_PABD
t_PALD
t_PABDD
ABCLK Delay
LRCLK Delay
ASDATA Delay
Min
Max
15
15
20
40
40
80
10
10
10
10
15
20
25
60
60
64 Ï« f_S
10
10
10
10
15
15
256 Ï« f_S
10
10
10
10
25
5
10
60
60
64 Ï« f_S
5
15
15
40
5
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Comments
To CCLK Rising
From CCLK Rising
To CCLK Rising
From CCLK Rising
From CLATCH Falling
From CCLK Falling
From CLATCH Rising
To DBCLK Rising
From DBCLK Rising
To DBCLK Rising
From DBCLK Rising
To DBCLK Rising
From DBCLK Rising
To DBCLK Rising
From DBCLK Rising
From MCLK Rising Edge
From ABCLK Falling Edge
From ABCLK Falling Edge
To ABCLK Rising
From ABCLK Rising
From ABCLK Falling Edge
From MCLK Rising Edge
From ABCLK Falling Edge
From ABCLK Falling Edge
–4–
REV. A