EVAL-AD1835AEB Datasheet, PDF (18/24 Pages) Analog Devices – 2 ADC, 8 DAC, 96 kHz, 24-Bit Codecs

AD1835A
CONTROL/STATUS REGISTERS
The AD1835A has 15 control registers, 13 of which are used to
set the operating mode of the part. The other two registers,
ADC Peak 0 and ADC Peak 1, are read-only and should not
be programmed. Each of the registers is 10 bits wide with the
exception of the ADC peak reading registers, which are six bits
wide. Writing to a control register requires a 16-bit data frame
to be transmitted. Bits 15 to 12 are the address bits of the
required register. Bit 11 is a read/write bit. Bit 10 is reserved
and should always be programmed to 0. Bits 9 to 0 contain the
10-bit value that is to be written to the register or, in the case of a
read operation, the 10-bit register contents. Figure 3 shows
the format of the SPI read and write operation.
DAC Control Registers
The AD1835A register map has 10 registers that are used to control
the functionality of the DAC section of the part. The function of
the bits in these registers is discussed in the following sections.
Sample Rate
These bits control the sample rate of the DACs. Based on a
24.576 MHz IMCLK, sample rates of 48 kHz, 96 kHz, and
192 kHz are available. The MCLK scaling bits in ADC
Control 3 should be programmed appropriately, based on the
master clock frequency.
Power-Down/Reset
This bit controls the power-down status of the DAC section. By
default, normal mode is selected, but by setting this bit, the digital
section of the DAC stage can be put into a low power mode, thus
reducing the digital current. The analog output section of the
DAC stage is not powered down.
DAC Data-Word Width
These two bits set the word width of the DAC data. Compact
disk (CD) compatibility may require 16 bits, but many modern
digital audio formats require 24-bit sample resolution.
DAC Data Format
The AD1835A serial data interface can be configured to be
compatible with a choice of popular interface formats, including
I²S, LJ, RJ, or DSP modes. Details of these interface modes are
given in the Serial Data Port section.
De-emphasis
The AD1835A provides built-in de-emphasis filtering for the
three standard sample rates of 32.0 kHz, 44.1 kHz, and 48 kHz.
Mute DAC
Each of the eight DACs in the AD1835A has its own independent
mute control. Setting the appropriate bit will mute the DAC
output. The AD1835A uses a clickless mute function that attenu-
ates the output to approximately –100 dB over a number of cycles.
Stereo Replicate
Setting this bit copies the digital data sent to the stereo pair
DAC1 to the three other stereo DACs in the system. This
allows all four stereo DACs to be driven by one digital data
stream. Note that in this mode, DAC data sent to the other
DACs is ignored.
DAC Volume Control
Each DAC in the AD1835A has its own independent volume
control. The volume of each DAC can be adjusted in 1024
linear steps by programming the appropriate register. The
default value for this register is 1023, which provides no
attenuation, i.e., full volume.
ADC Control Registers
The AD1835A register map has five registers that are used to
control the functionality and read the status of the ADCs. The
function of the bits in each of these registers is discussed in the
following sections.
ADC Peak Level
These two registers store the peak ADC result from each chan-
nel when the ADC peak readback function is enabled. The peak
result is stored as a 6-bit number from 0 dB to –63 dB in 1 dB
steps. The value contained in the register is reset once it has
been read, allowing for continuous level adjustment as required.
Note that the ADC peak level registers use the six most signifi-
cant bits in the register to store the results.
Sample Rate
This bit controls the sample rate of the ADCs. Based on a
24.576 MHz IMCLK, sample rates of 48 kHz and 96 kHz are
available. The MCLK scaling bits in ADC Control 3 should
be programmed appropriately based on the master clock
frequency.
ADC Power-Down
This bit controls the power-down status of the ADC section and
operates in a manner similar to the DAC power-down.
High-Pass Filter
The ADC signal path has a digital high-pass filter. Enabling this
filter will remove the effect of any dc offset in the analog input
signal from the digital output codes.
ADC Data-Word Width
These two bits set the word width of the ADC data.
ADC Data Format
The AD1835A serial data interface can be configured to be
compatible with a choice of popular interface formats, including
I²S, LJ, RJ, or DSP modes.
Master/Slave Auxiliary Mode
When the AD1835A is operating in the auxiliary mode, the
auxiliary ADC control pins, AUXBCLK and AUXLRCLK,
which connect to the external ADCs, can be set to operate as a
master or slave. If the pins are set in slave mode, one of the
external ADCs should provide the LRCLK and BCLK signals.
ADC Peak Readback
Setting this bit enables ADCs peak reading. See the ADCs section
for more information.
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REV. A