EVAL-AD1835AEB Datasheet, PDF (21/24 Pages) Analog Devices – 2 ADC, 8 DAC, 96 kHz, 24-Bit Codecs

AD1835A
CASCADE MODE
Dual AD1835A Cascade
The AD1835A can be cascaded to an additional AD1835A
which, in addition to six external stereo ADCs, can be used to
create a 32-channel audio system with 16 inputs and 16 outputs.
The cascade is designed to connect to a SHARC DSP and oper-
ates in a time division multiplexing (TDM) format. Figure 16
shows the connection diagram for cascade operation. The digital
interface for both parts must be set to operate in Auxiliary 512
mode by programming ADC Control Register 2. AD1835A No. 1
is set as a master device by connecting the M/S pin to DGND
and AD1835A No. 2 is set as a slave device by connecting the
M/S to ODVDD. Both devices should be run from the same
MCLK and PD/RST signals to ensure that they are synchronized.
With Device 1 set as a master it will generate the frame-sync and
bit clock signals. These signals are sent to the SHARC and
Device 2, ensuring that both know when to send and receive data.
The cascade can be thought of as two 256 bit shift registers, one for
each device. At the beginning of a sample interval, the shift regis-
ters contain the ADC results from the previous sample interval.
The first shift register (Device 1) clocks data into the SHARC and
clocks in data from the second shift register (Device 2). While this
is happening, the SHARC is sending DAC data to the second shift
register. By the end of the sample interval, all 512 bits of ADC data
in the shift registers will have been clocked into the SHARC and
replaced by DAC data, which is subsequently written to the DACs.
Figure 17 shows the timing diagram for the cascade operation.
AUX ADC
(SLAVE)
AUX ADC
(SLAVE)
AUX ADC
(SLAVE)
AUX ADC
(SLAVE)
AUX ADC
(SLAVE)
AUX ADC
(SLAVE)
AD1835A No. 1
(MASTER)
AD1835A No. 2
(SLAVE)
SHARC
(SLAVE)
DRx
RFSx
RCLKx
TFSx
TCLKx
DTx
ASDATA
ALRCLK
ABCLK
DSDATA
ASDATA
ALRCLK
ABCLK
Figure 16. Dual AD1835A Cascade
DSDATA
TFSx/
RFSx
DTx
DRx
256 ABCLKs
256 ABCLKs
AD1835A No. 1 DACs
AD1835A No. 2 DACs
L1 L2 L3 L4 R1 R2 R3 R4 L1 L2 L3 L4 R1 R2 R3 R4
AD1835A No. 1 ADCs
AD1835A No. 2 ADCs
L1 L2 L3 L4 R1 R2 R3 R4 L1 L2 L3 L4 R1 R2 R3 R4
ABCLK
DTx
DRx
MSB MSB – 1
MSB MSB – 1
LSB
LSB
DON’T CARE
32 ABCLKs
Figure 17. Dual AD1835A Cascade Timing
REV. A
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