EVAL-AD1835AEB Datasheet, PDF (12/24 Pages) Analog Devices – 2 ADC, 8 DAC, 96 kHz, 24-Bit Codecs

AD1835A
MCLK
12.288MHz
DAC I/P
48kHz/96kHz/192kHz
INTERPOLATION
FILTER
DAC ENGINE
Σ-∆
MODULATOR
CLOCK SCALING
؋1
؋2
؋2/3
IMCLK = 24.576MHz
DAC
ADC O/P
48kHz/96kHz
OPTIONAL
HPF
ADC ENGINE
DECIMATOR /
FILTER
Σ-∆
MODULATOR
Figure 2. Modulator Clocking Scheme
ANALOG
OUTPUT
ANALOG
INPUT
CLATCH
t_CLS
t_CCP
CCLK
CIN
D15
D14
COUT t_COE
t_CCH t_CCL
t_CDS t_CDH
D9
D8
D9
D8
t_COD
Figure 3. Format of SPI Timing
t_CLH
t_COTS
D0
D0
Table III. ADC Sample Rate Settings
Power Supply and Voltage Reference
Sample Rate
ADC Control 1 Register
The AD1835A is designed for 5 V supplies. Separate power supply
pins are provided for the analog and digital sections. These pins
IMCLK/512
IMCLK/256
1100000xx0xxxxxx (48 kHz)
1100000xx1xxxxxx (96 kHz)
should be bypassed with 100 nF ceramic chip capacitors, as
close to the pins as possible, to minimize noise pickup. A bulk
aluminum electrolytic capacitor of at least 22 ␮F should also be
To maintain the highest performance possible, the clock jitter of
the master clock signal should be limited to less than 300 ps
rms, measured using the edge-to-edge technique. Even at these
provided on the same PC board as the codec. For critical applica-
tions, improved performance will be obtained with separate
supplies for the analog and digital sections. If this is not pos-
levels, extra noise or tones may appear in the DAC outputs if
the jitter spectrum contains large spectral peaks. It is highly
sible, it is recommended that the analog and digital supplies be
isolated by two ferrite beads in series with the bypass capacitor
recommended that the master clock be generated by an inde-
of each supply. It is important that the analog supply be as clean
pendent crystal oscillator. In addition, it is especially important as possible.
that the clock signal not be passed through an FPGA or other
large digital chip before being applied to the AD1835A. In most
cases, this will induce clock jitter due to the fact that the clock
signal is sharing common power and ground connections with
unrelated digital output signals.
RESET and Power-Down
PD/RST will power down the chip and set the control registers
to their default settings. After PD/RST is de-asserted, an
initialization routine will run inside the AD1835A to clear all
memories to zero. This initialization lasts approximately 20
LRCLK intervals. During this time, it is recommended that no
SPI writes occur.
The internal voltage reference is brought out on the FILTR pin
and should be bypassed as close as possible to the chip, with a
parallel combination of 10 µF and 100 nF. The reference volt-
age may be used to bias external op amps to the common-mode
voltage of the analog input and output signal pins. The current
drawn from the V_REF pin should be limited to less than 50 ␮A.
Serial Control Port
The AD1835A has an SPI compatible control port to permit
programming the internal control registers for the ADCs and
DACs and for reading the ADC signal levels from the internal
peak detectors. The SPI control port is a 4-wire serial control port.
–12–
REV. A