EVAL-AD1835AEB Datasheet, PDF (16/24 Pages) Analog Devices – 2 ADC, 8 DAC, 96 kHz, 24-Bit Codecs

AD1835A
Pin Name
ASDATA (O)
DSDATA1 (I)
DSDATA2 (I)/AAUXDATA1 (I)
DSDATA3 (I)/AAUXDATA2 (I)
DSDATA4 (I)/AAUXDATA3 (I)
ALRCLK (O)
ABCLK (O)
DLRCLK (I)/AUXLRCLK(I/O)
DBCLK (I)/AUXBCLK(I/O)
Table IV. Pin Function Changes in Auxiliary Mode
I²S Mode
I²S Data Out, Internal ADC
I²S Data In, Internal DAC1
I²S Data In, Internal DAC2
I²S Data In, Internal DAC3
I²S Data In, Internal DAC4
LRCLK for ADC
BCLK for ADC
LRCLK In/Out Internal DACs
BCLK In/Out Internal DACs
Auxiliary Mode
TDM Data Out to SHARC.
TDM Data In from SHARC.
AUX-I²S Data In 1 (from External ADC).
AUX-I²S Data In 2 (from External ADC).
AUX-I²S Data In 3 (from External ADC).
TDM Frame Sync Out to SHARC (FSTDM).
TDM BCLK Out to SHARC.
AUX LRCLK In/Out. Driven by external LRCLK from ADC in
slave mode. In master mode, driven by MCLK/512.
AUX BCLK In/Out. Driven by external BCLK from ADC
in slave mode. In master mode, driven by MCLK/8.
FSTDM
BCLK
TDM
ASDATA1
TDM (OUT)
ASDATA
DSDATA1
TDM (IN)
DSDATA1
MSB TDM
1ST
CH
MSB TDM
8TH
CH
INTERNAL
ADC L1
32
MSB TDM
1ST
CH
AUX_ADC L2 AUX_ADC L3 AUX_ADC L4
INTERNAL
ADC R1
AUX_ADC R2 AUX_ADC R3 AUX_ADC R4
MSB TDM
8TH
CH
INTERNAL
DAC L1
32
INTERNAL
DAC L2
INTERNAL
DAC L3
INTERNAL
DAC L4
INTERNAL
DAC R1
INTERNAL
DAC R2
INTERNAL
DAC R3
INTERNAL
DAC R4
AUX
LRCLK I²S
(FROM AUX ADC No. 1)
AUX
BCLK I²S
(FROM AUX ADC No. 1)
AAUXDATA1 (IN)
(FROM AUX ADC No. 1)
AAUXDATA2 (IN)
(FROM AUX ADC No. 2)
LEFT
I²S – MSB LEFT
I²S – MSB LEFT
RIGHT
I²S – MSB RIGHT
I²S – MSB RIGHT
AAUXDATA3 (IN)
(FROM AUX ADC No. 3)
I²S – MSB LEFT
AUX BCLK FREQUENCY IS 64 ؋ FRAME RATE; TDM BCLK FREQUENCY IS 256 ؋ FRAME RATE.
Figure 13. Auxiliary Mode Timing
I²S – MSB RIGHT
–16–
REV. A