PAC5250_17 Datasheet, PDF (40/70 Pages) Active-Semi, Inc – Power Application Controller

PAC5250
Power Application Controller
Figure 12-3. High-Side Switching Transients and Optional Circuitry
V ≤ 625V
DXBx
DXBx
DXHx
V
P
V
IN
DXSx
V
DXBx
dV/dt
dV/dt
V
DXSx
V ≥ -10V
DXSx
(a) High-Side Switching Transients
PAC5250
DRLx
(b) Optional Transient Protection and Slew Rate Control
12.3.4. Open-Drain Drivers
The OMx pin is a 23V open-drain driver output controlled by a register bit. OMx is capable of driving 40mA. The OMx pin
is switched to VSSP with 17Ω impedance in the on state when the corresponding bit is '1', and is in the high-impedance off
state when the corresponding bit is '0'.
12.3.5. Power Drivers Control
All power drivers are initially disabled from power-on-reset. To enable the power drivers, the microprocessor must first set
the driver enable bit to '1'. The gate drivers controlled by the microcontroller ports and PWM signals according to Table 22,
with configurable delays as shown in Table 22. The OMx open-drain drivers are controlled by their corresponding register
bits. Refer to the PAC application notes and user guide for additional information on power drivers control programming.
Table 22. Microcontroller Port and PWM to Power Driver Mapping
PART
NUMBER
PWMA0
PWMA1
PWMA2
PWMA3/
PWMA4/
PWMB0
PWMA5/
PWMC0
PAC5250
DRL0
DRL1
DRL2
DRL3
DRL4
PWMA6/
PWMD0
DRL5
PWMA4/
PWMB0
DXH0
PWMA5/
PWMA7/
PWMC1
DXH1
PWMA6/
PWMD0
DXH2
Table 23. Power Driver Delay Configuration
DELAY
SETTING
RISING
DRLx
Default Setting
130ns
01b Setting
170ns
10b Setting
230ns
11b Setting
360ns
FALLING
140ns
180ns
250ns
380ns
RISING
200ns
DXHx
FALLING
240ns
- 40 -
Rev 1.7‒April 15, 2016