ACE25C400 Datasheet, PDF (8/31 Pages) ACE Technology Co., LTD. – 4MB Serial Flash Memory

ACE25C400
4MB Serial Flash Memory
Status Register
The Read Status Register instruction can be used to provide status on the availability of the Flash
memory array, if the device is write enabled or disabled, the state of write protection, Security Sector
lock status. The Write Status Register instruction can be used to configure the device write protection
features and Security Sector OTP lock. Write access to the Status Register is controlled by the state
of the non-volatile Status Register Protect bit (SRP), the Write Enable instruction, and the WP# pin.
Factory default for all Status Register bits are 0.
Figure 4 Status Register
WIP Bit
WIP is a read only bit in the status register (S0) that is set to a 1 state when the device is executing a
Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register. During this time the
device will ignore further instructions except for the Read Status Register and Erase/Program
Suspend instruction (see t_W, t_PP, t_SE, t_BE, and t_CE in “12.6 AC Electrical Characteristics”). When the
program, erase or write status register (or security sector) instruction has completed, the WIP bit will
be cleared to a 0 state indicating the device is ready for further instructions.
Write Enable Latch bit (WEL)
Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to 1 after executing a
Write Enable Instruction. The WEL status bit is cleared to 0 when the device is write disabled. A write
disable state occurs upon power-up or after any of the following instructions: Write Disable, Page
Program, Sector Erase, Block Erase, Chip Erase, Write Status Register.
Block Protect Bits (BP2, BP1,BP0)
The Block Protect Bits (BP2, BP1, BP0) are non-volatile read/write bits in the status register (S4, S3,
and S2) that provide Write Protection control and status. Block Protect bits can be set using the Write
Status Register Instruction (see t_W in “12.6 AC Electrical Characteristics”). All, none or a portion of the
memory array can be protected from Program and Erase instructions (see Table 2 Status Register
Memory Protection). The factory default setting for the Block Protection Bits is 0, none of the array
protected.
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