ACE25C400 Datasheet, PDF (7/31 Pages) ACE Technology Co., LTD. – 4MB Serial Flash Memory

ACE25C400
4MB Serial Flash Memory
HOLD# operation to avoid resetting the internal logic state of the device.
Figure 3 Hold condition waveform
Write Protection
Applications that use non-volatile memory must take into consideration the possibility of noise and
other adverse system conditions that may compromise data integrity. To address this concern, the
ACE25C400 provides several means to protect the data from inadvertent writes.
Write Protect Features
 Device resets when VCC is below threshold
 Time delay write disable after Power-up
 Write enable/disable instructions and automatic write disable after erase or program
 Software and Hardware (WP# pin) write protection using Status Register
 Write Protection using Power-down instruction
 Lock Down write protection for Status Register until the next power-up
 One Time Program (OTP) write protection for array and Security Sectors using Status Register.
Upon power-up or at power-down, the ACE25C400 will maintain a reset condition while VCC is
below the threshold value of VWI, (See “12.3 Power-up Timing” and Figure 23). While reset, all
operations are disabled and no instructions are recognized. During power-up and after the VCC
voltage exceeds VWI, all program and erase related instructions are further disabled for a time delay
of t_PUW. This includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase and
the Write Status Register instructions. Note that the chip select pin (CS#) must track the VCC supply
level at power-up until the VCC-min level and t_VSL time delay is reached. If needed a pull-up resister
on CS# can be used to accomplish this.
After power-up the device is automatically placed in a write-disabled state with the Status Register
Write Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page
Program, Sector Erase, Block Erase, Chip Erase or Write Status Register instr uction will be accepted.
After completing a program, erase or write instruction the Write Enable Latch (WEL) is automatically
cleared to a write-disabled state of 0.
Software controlled write protection is facilitated using the Write Status Register inst ruction and
setting the Status Register Protect (SRP) and Block Protect (BP2, BP1 and BP0) bits. These settings
allow a portion as small as a 4KB sector or the entire memory array to be configured as read only.
Used in conjunction with the Write Protect (W P#) pin, changes to the Status Register can be enabled
or disabled under hardware control. See Status Register section for further information. Additionally,
the Power-down instruction offers an extra level of write protection as all instructions are ignor ed
except for the Release Power-down instruction.
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