ACE25C400 Datasheet, PDF (15/31 Pages) ACE Technology Co., LTD. – 4MB Serial Flash Memory

ACE25C400
4MB Serial Flash Memory
Figure 11 Fast read dual output instruction
Fast Read Dual I/O (BBh)
The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two
I/O pins, DQ₀ and DQ₁. It is similar to the Fast Read Dual Output (3Bh) instruction but with the
capability to input the Address bits A23-A0 two bits per clock. This reduced instruction overhead may
allow for code execution (XIP) directly from the Dual SPI in some applications.
Fast Read Dual I/O with “Continuous Read Mode”
The Fast Read Dual I/O instruction can further reduce instruction overhead thro ugh setting the
“Continuous Read Mode” bits (M7-0) after the input Address bits A23-A0, as shown in Figure 12. The
upper nibble of the (M7-4) controls the length of the next Fast Read Dual I/O instruction through the
inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t
care (“x”). However, the DQ pins should be high-impedance prior to the falling edge of the first data
out clock.
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Dual I/O instruction (after
CS# is raised and then lowered) does not require the BBh instruction code, as shown in Figure 13.
This reduces the instruction sequence by eight clocks and allows the Read address to be immediately
entered after CS# is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0),
the next instruction (after CS# is raised and then lowered) requires the first byte instruction code, thus
returning to normal operation. It is recommended to input FFFFh on DQ₀ for the next.
VER 1.2 15