ACE25C400 Datasheet, PDF (19/31 Pages) ACE Technology Co., LTD. – 4MB Serial Flash Memory

ACE25C400
4MB Serial Flash Memory
Figure 16 Block erase instruction
Chip Erase (CE) (C7h / 60h)
The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A
Write Enable instruction must be executed before the device will accept the Chip Erase Instruction
(Status Register bit WEL must equal 1). The instruction is initiated by driving the CS# pin low and
shifting the instruction code “C7h” or “60h”. The Chip Erase instruction sequence is shown in Figure
17.
The CS# pin must be driven high after the eighth bit has been latched. If this is not done the Ch ip
Erase instruction will not be executed. After CS# is driven high, the self-timed Chip Erase instruction
will commence for a time duration of t_CE (See “12.6 AC Electrical Characteristics”). While the Chip
Erase cycle is in progress, the Read Status Register instruction may still be accessed to check the
status of the WIP bit. The WIP bit is a 1 during the Chip Erase cycle and becomes a 0 when finished
and the device is ready to accept other instructions again. After the Chip Erase cycle has finished the
Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Chip Erase instruction will not
be executed if any page is protected by the Block Protect (BP2, BP1, and BP0) bits.
Figure 17 Chip erase instruction
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