ACE25C400 Datasheet, PDF (6/31 Pages) ACE Technology Co., LTD. – 4MB Serial Flash Memory

ACE25C400
4MB Serial Flash Memory
Device Operations
Standard SPI
The ACE25C400 is accessed through an SPI compatible bus consisting of four signals: Serial Clock
(CLK), Chip Select (CS#), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI
instructions use the DI input pin to serially write instructions, addr esses or data to the device on the
rising edge of CLK. The DO output pin is used to read data or status from the device on the falling
edge of CLK.
SPI bus operation Mode 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0
and Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in standby and
data is not being transferred to the Serial Flash. For Mode 0, the CLK signal is normally low on the
falling and rising edges of CS#. For Mode 3, the CLK signal is normally high on the falling and rising
edges of CS#.
Figure 2 The difference between Mode 0 and Mode 3
Dual SPI
The ACE25C400 supports Dual SPI operation when using instructions such as “Fast Read Dual
Output (3Bh)” and “Fast Read Dual I/O (BBh)”. These instructions allow data to be transferred to or
from the device at two to three times the rate of ordinary Serial Flash devices. The Dual SPI Read
instructions are ideal for quickly downloading code to RAM upon power-up (code-shadowing) or for
executing non-speed- critical code directly from the SPI bus (XIP). When using Dual SPI instructions,
the DI and DO pins become bidirectional I/O pins: DQ₀ and DQ₁.
Hold
For Standard SPI and Dual SPI operations, the HOLD# signal allows the ACE25C400 operation to
be paused while it is actively selected (when CS# is low). The HOLD# function may be useful in cases
where the SPI data and clock signals are shared with other devices. For example, consider if the page
buffer was only partially written when a priority interrupt requires use of the SPI bus. In this case the
HOLD# function can save the state of the instruction and the data in the buffer so programming can
resume where it left off once the bus is available again.
To initiate a HOLD# condition, the device must be selected with CS# low. A HOLD# condition will
activate on the falling edge of the HOLD# signal if the CLK signal is already low. If the CLK is not
already low the HOLD# condition will activate after the next falling edge of CLK. The HOLD# condition
will terminate on the rising edge of the HOLD# signal if the CLK signal is already low. If the CLK is not
already low the HOLD# condition will terminate after the next falling edge of CLK. During a HOLD#
condition, the Serial Data Output (DO) is high impedance, and Serial Data Input (DI) and Serial Clock
(CLK) are ignored. The Chip Select (CS#) signal should be kept active (low) for the full duration of the
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