ACE25C400 Datasheet, PDF (12/31 Pages) ACE Technology Co., LTD. – 4MB Serial Flash Memory

ACE25C400
4MB Serial Flash Memory
Read status register (RDSR) (05h)
The Read Status Register instructions allow the 8-bit Status Registers to be read. The instruction is
entered by driving CS# low and shifting the instruction code “05h” into the DI pin on the rising edge of
CLK. The status register bits are then shifted out on the DO pin at the falling edge of CLK with most
significant bit (MSB) first as shown in Figure 7. The Status Register bits are shown in Figure 4 and
include the WIP, WEL, BP2-BP0 and SRP bits.
The Read Status Register instruction may be used at any time, even while a Program, Erase or Write
Status Register cycle is in progress. This allows the WIP status bit to be checked to determine when
the cycle is complete and if the device can accept another instruction. The Status Register can be
read continuously. The instruction is completed by driving CS# high.
Figure 7 Read status register instruction
Write Status Register (WRSR) (01h)
The Write Status Register (WRSR) instruction allows the Status Register to be written. Only
non-volatile Status Register bits SRP, BP2, BP1, BP0 can be written to. All other Status Register bit
locations are read-only and will not be affected by the Write Status Register (WRSR) instruction . The
Status Register bits are shown in Figure 4, and described in 10 Status Register.
To write non-volatile Status Register bits, a standard Write Enable (06h) instruction must previously
have been executed for the device to accept the Write Status Register (WRSR) instruction (Status
Register bit WEL must equal 1). Once write enabled, the instruction is entered by driving CS# low,
sending the instruction code “01h”, and then writing the status register data byte as illustrated in
Figure 8.
To complete the Write Status Register (WRSR) instruction, the CS# pin must be driven high after the
eighth or sixteenth bit of data that is clocked in. If this is not done the Write Status Register (WRSR)
instruction will not be executed.
During non-volatile Status Register write operation (06h combined with 01h), after CS# is driven high,
the self-timed Write Status Register cycle will commence for a time duration of t_W (See “12.6 AC
Electrical Characteristics”). While the Write Status Register cycle is in progres s, the Read Status
Register instruction may still be accessed to check the status of the WIP bit. The WIP bit is a 1 during
the Write Status Register cycle and a 0 when the cycle is finished and ready to accept other
instructions again. After the Write Status Register cycle has finished, the Write Enable Latch (WEL) bit
in the Status Register will be cleared to 0.
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