ACE25C200 Datasheet, PDF(6/32 Page) ACE Technology Co., LTD.

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ACE25C200 Datasheet, PDF (6/32 Pages) ACE Technology Co., LTD. – 2MB Serial Flash Memory

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ACE25C200

2MB Serial Flash Memory

Dual SPI

The ACE25C200 supports Dual SPI operation when using instructions such as âFast Read Dual

Output (3Bh)â and âFast Read Dual I/O (BBh)â. These instructions allow data to be transferred to or

from the device at two to three times the rate of ordinary Serial Flash devices. The Dual SPI Read

instructions are ideal for quickly downloading code to RAM upon power-up (code-shadowing) or for

executing non-speed- critical code directly from the SPI bus (XIP). When using Dual SPI instructions,

the DI and DO pins become bidirectional I/O pins: DQ0 and DQ1.

Hold

For Standard SPI and Dual SPI operations, the HOLD# signal allows the ACE25C200 operation to

be paused while it is actively selected (when CS# is low). The HOLD# function may be useful in cases

where the SPI data and clock signals are shared with other devices. For example, consider if the page

buffer was only partially written when a priority interrupt requires use of the SPI bus. In this case the

HOLD# function can save the state of the instruction and the data in the buffer so programming can

resume where it left off once the bus is available again.

To initiate a HOLD# condition, the device must be selected with CS# low. A HOLD# condition will

activate on the falling edge of the HOLD# signal if the CLK signal is already low. If the CLK is not

already low the HOLD# condition will activate after the next falling edge of CLK. The HOLD# condition

will terminate on the rising edge of the HOLD# signal if the CLK signal is already low. If the CLK is not

already low the HOLD# condition will terminate after the next falling edge of CLK. During a HOLD#

condition, the Serial Data Output (DO) is high impedance, and Serial Data Input (DI) and Serial Clock

(CLK) are ignored. The Chip Select (CS#) signal should be kept active (low) for the full duration of the

HOLD# operation to avoid resetting the internal logic state of the device.

Figure 3 Hold condition waveform

VER 1.2 6

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