ACE25C200 Datasheet, PDF (18/32 Pages) ACE Technology Co., LTD. – 2MB Serial Flash Memory

ACE25C200
2MB Serial Flash Memory
As with the write and erase instructions, the CS# pin must be driven high after the eighth bit o f the
last byte has been latched. If this is not done the Page Program instruction will not be executed. After
CS# is driven high, the self-timed Page Program instruction will commence for a time duration of t_PP
(See “12.6 AC Electrical Characteristics”). While the Page Program cycle is in progress, the Read
Status Register instruction may still be accessed for checking the status of the WIP bit. The WIP bit is
a 1 during the Page Program cycle and becomes a 0 when the cycle is finished and the device is
ready to accept other instructions again. After the Page Program cycle has finished the Write Enable
Latch (WEL) bit in the Status Register is cleared to 0. The Page Program instruction will not be
executed if the addressed page is protected by the Block Protect (BP2, BP1, and BP0) bits.
Figure 14 Page program instruction
Sector Erase (20h)
The Sector Erase instruction sets all memory within a specified sector (4K-bytes) to the erased state
of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Sector
Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the
CS# pin low and shifting the instruction code “20h” followed a 24-bit sector address A23-A0 (see
Figure 1). The Sector Erase instruction sequence is shown in Figure 15 . The CS# pin must be
driven high after the eighth bit of the last byte has been latched. If this is not
done the Sector Erase instruction will not be executed. After CS# is driven high, the s elf-timed
Sector Erase instruction will commence for a time duration of t_SE (See “12.6 AC Electrical
Characteristics”). While the Sector Erase cycle is in progress, the Read Status Register instruction
may still be accessed for checking the status of the WIP bit. The WIP bit is a 1 during the Sector Erase
cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions
again. After the Sector Erase cycle has finished the Write Enable Latch (WEL) bit in the Status
Register is cleared to 0.
The Sector Erase instruction will not be executed if the addressed page is protected by the Block
Protect (BP2, BP1, and BP0) bits (see Table 2 Status Register Memory Protection table).
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