ACE25C200 Datasheet, PDF (15/32 Pages) ACE Technology Co., LTD. – 2MB Serial Flash Memory

ACE25C200
2MB Serial Flash Memory
Similar to the Fast Read instruction, the Fast Read Dual Output instruction can operate at the
highest possible frequency of FR (see “12.6 AC Electrical Characteristics”). This is accomplished by
adding eight “dummy” clocks after the 24-bit address as shown in Figure 11. The dummy clocks allow
the device's internal circuits additional time for setting up the initial address. The input data during the
dummy clocks is “don’t care”. However, the DQ₀ pin should be high-impedance prior to the falling
edge of the first data out clock.
Figure 11 Fast read dual output instruction
Fast Read Dual I/O (BBh)
The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two
I/O pins, DQ₀ and DQ₁. It is similar to the Fast Read Dual Output (3Bh) instruction but with the
capability to input the Address bits A23-A0 two bits per clock. This reduced instruction overhead may
allow for code execution (XIP) directly from the Dual SPI in some applications.
Fast Read Dual I/O with “Continuous Read Mode”
The Fast Read Dual I/O instruction can further reduce instruction overhead through setting the
“Continuous Read Mode” bits (M7-0) after the input Address bits A23-A0, as shown in Figure 12. The
upper nibble of the (M7-4) controls the length of the next Fast Read Dual I/O instruction through the
inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t
care (“x”). However, the DQ pins should be high-impedance prior to the falling edge of the first data
out clock.
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