ACE25C200 Datasheet, PDF (5/32 Pages) ACE Technology Co., LTD. – 2MB Serial Flash Memory

ACE25C200
2MB Serial Flash Memory
Block (64KB)
3
2
1
0
Sector (4KB)
63
…
48
47
…
32
31
…
16
15
…
2
1
0
Address Range
03F000h
03FFFFh
…
…
030000h
030FFFh
02F000h
02FFFFh
…
…
020000h
020FFFh
01F000h
01FFFFh
…
…
010000h
010FFFh
00F000h
00FFFFh
…
…
002000h
002FFFh
001000h
001FFFh
000000h
000FFFh
Device Operations
Standard SPI
The ACE25C200 is accessed through an SPI compatible bus consisting of four signals: Serial Clock
(CLK), Chip Select (CS#), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI
instructions use the DI input pin to serially write instructions, addresses or data to the device on the
rising edge of CLK. The DO output pin is used to read data or status from the device on the falling
edge of CLK.
SPI bus operation Mode 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0
and Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in standby and
data is not being transferred to the Serial Flash. For Mode 0, the CLK signal is normally low on the
falling and rising edges of CS#. For Mode 3, the CLK signal is normally high on the falling and rising
edges of CS#.
Figure 2 The difference between Mode 0 and Mode 3
VER 1.2 5