OMAP3503DCBBA Datasheet, PDF (52/264 Pages) Texas Instruments – OMAP3515 and OMAP3503 Applications Processors

OMAP3515, OMAP3503
SPRS505H – FEBRUARY 2008 – REVISED OCTOBER 2013
www.ti.com
Table 2-2. Ball Characteristics (CBC Pkg.)⁽¹⁾ (continued)
BALL
BALL TOP PIN NAME
BOTTOM [1]
[2]
[3]
MODE [4]
M1
K1
gpmc_nwe
0
AC6
Y5
gpmc_nwp
0
AC11
gpio_62
4
safe_mode
7
Y10
gpmc_wait0
0
AC8
Y8
gpmc_wait1
0
gpio_63
4
safe_mode
7
B3
NA
gpmc_wait2
0
gpio_64
4
safe_mode
7
C6
NA
gpmc_wait3
0
W19
sys_ndmareq
1
1
gpio_65
4
safe_mode
7
NA
hsusb0_clk
0
V20
Y20
V18
W20
W17
Y18
Y19
Y17
gpio_120
4
safe_mode
7
NA
hsusb0_data
0
0
uart3_tx_irtx
2
gpio_125
4
safe_mode
7
NA
hsusb0_data
0
1
uart3_rx_irrx
2
gpio_130
4
safe_mode
7
NA
hsusb0_data
0
2
uart3_rts_sd
2
gpio_131
4
safe_mode
7
NA
hsusb0_data
0
3
uart3_cts_rct
2
x
gpio_169
4
safe_mode
7
NA
hsusb0_data
0
4
gpio_188
4
safe_mode
7
NA
hsusb0_data
0
5
gpio_189
4
safe_mode
7
NA
hsusb0_data
0
6
gpio_190
4
safe_mode
7
NA
hsusb0_data
0
7
TYPE [5]
O
O
IO
-
I
I
IO
-
I
IO
-
I
I
IO
-
I
IO
-
IO
O
IO
-
IO
I
IO
-
IO
O
IO
-
IO
IO
IO
-
IO
IO
-
IO
IO
-
IO
IO
-
IO
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
RESET REL.
MODE [8]
POWER [9]
1
1
0
vdds
L
0
0
vdds
HYS [10]
No
Yes
BUFFER
STRENG TH
(mA) [11]
4 ⁽⁶⁾
4 ⁽⁶⁾
PULLUP
/DOWN
TYPE [12]
NA
PU100/
PD100
IO CELL [13]
LVCMOS
LVCMOS
H
H
0
vdds
Yes
4 ⁽⁶⁾
PU100/
LVCMOS
PD100
H
H
7
vdds
Yes
4 ⁽⁶⁾
PU100/
LVCMOS
PD100
H
H
7
vdds
Yes
4 ⁽⁶⁾
PU100/
LVCMOS
PD100
H
H
7
vdds
Yes
4 ⁽⁶⁾
PU100/
LVCMOS
PD100
L
L
7
vdds
Yes
4 ⁽⁷⁾
PU100/
LVCMOS
PD100
L
L
7
vdds
Yes
4 ⁽⁷⁾
PU100/
LVCMOS
PD100
L
L
7
vdds
Yes
4 ⁽⁷⁾
PU100/
LVCMOS
PD100
L
L
7
vdds
Yes
4 ⁽⁷⁾
PU100/
LVCMOS
PD100
L
L
7
vdds
Yes
4 ⁽⁷⁾
PU100/
LVCMOS
PD100
L
L
7
vdds
Yes
4 ⁽⁷⁾
PU100/
LVCMOS
PD100
L
L
7
vdds
Yes
4 ⁽⁷⁾
PU100/
LVCMOS
PD100
L
L
7
vdds
Yes
4 ⁽⁷⁾
PU100/
LVCMOS
PD100
L
L
7
vdds
Yes
4 ⁽⁷⁾
PU100/
LVCMOS
PD100
(7) The capacity load range is [2 pf to 6 pF].
52
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