OMAP3503DCBBA Datasheet, PDF (184/264 Pages) Texas Instruments – OMAP3515 and OMAP3503 Applications Processors

OMAP3515, OMAP3503
SPRS505H – FEBRUARY 2008 – REVISED OCTOBER 2013
www.ti.com
6.5 Video Interfaces
6.5.1 Camera Interface
The camera subsystem provides the system interfaces and the processing capability to connect supported
YCbCr Interfaces to the OMAP3515/03 device. The camera subsystem supports up to two simultaneous
pixel flows but only one of them can use supported video processing hardware:
• PARALLEL : the parallel interface data must go through the video processing hardware.
6.5.1.1 Parallel Camera Interface Timing
The parallel camera interface is a 12-bit interface which can be used in two modes:
1. SYNC mode: progressive and interlaced image sensor modules for 8-, 10-, 11-, and 12-bit data. The
pixel clock can be up to 75 MHz in 12-bit mode. The pixel clock can be up to 130 MHz in 8-bit packed
mode.
2. ITU mode provides an ITU-R BT 656 compatible data stream with progressive image sensor modules
only in 8- and 10-bit configurations. The pixel clock can be up to 75 MHz.
6.5.1.1.1 SYNC Normal Mode
6.5.1.1.1.1 12-Bit SYNC Normal – Progressive Mode
Table 6-23 and Table 6-24 assume testing over the recommended operating conditions and electrical
chaDSI Timing Conditionsracteristic conditions (see Figure 6-23).
Table 6-22. ISP Timing Conditions – 12-Bit SYNC Normal – Progressive Mode
TIMING CONDITION PARAMETER
Input Conditions
t_R
t_F
Output Condition
Input signal rise time
Input signal fall time
C_LOAD
Output load capacitance
VALUE
2.7
2.7
8.6
UNIT
ns
ns
pF
NO.
ISP17
ISP18
ISP18
ISP19
ISP20
ISP21
ISP22
ISP23
Table 6-23. ISP Timing Requirements – 12-Bit SYNC Normal – Progressive Mode⁽¹⁾
t_c(pclk)
t_W(pclkH)
t_W(pclkL)
t_dc(pclk)
t_j(pclk)
t_su(dV-pclkH)
t_h(pclkH-dV)
t_su(dV-vsH)
t_h(pclkH-vsV)
t_su(dV-hsH)
PARAMETER
Cycle time⁽²⁾, cam_pclk period
Typical pulse duration, cam_pclk high
Typical pulse duration, cam_pclk low
Duty cycle error, cam_pclk
Cycle jitter⁽⁴⁾, cam_pclk
Setup time, cam_d[11:0] valid before cam_pclk rising
edge
Hold time, cam_d[11:0] valid after cam_pclk rising
edge
Setup time, cam_vs valid before cam_pclk rising
edge
Hold time, cam_vs valid after cam_pclk rising edge
Setup time, cam_hs valid before cam_pclk rising
edge
1.15 V
MIN
MAX
13.3
0.5*P ⁽³⁾
0.5*P ⁽³⁾
667
133
1.82
1.82
1.82
1.82
1.82
1.0 V
MIN
MAX
22.2
0.5*P ⁽³⁾
0.5*P ⁽³⁾
1111
200
3.25
3.25
3.25
3.25
3.25
UNIT
ns
ns
ns
ps
ps
ns
ns
ns
ns
ns
(1) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified.
(2) Related with the input maximum frequency supported by the ISP module.
(3) P = cam_pclk period in ns
(4) Maximum cycle jitter supported by cam_pclk input clock.
184 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS
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