OMAP3503DCBBA Datasheet, PDF (229/264 Pages) Texas Instruments – OMAP3515 and OMAP3503 Applications Processors

OMAP3515, OMAP3503
www.ti.com
SPRS505H – FEBRUARY 2008 – REVISED OCTOBER 2013
6.6.5.2 I²C High-Speed Mode
Table 6-108. I²C HighSpeed Mode Timings^{(1) (2)}
NO.
PARAMETER
CB = 100 pF MAX
CB = 400 pF MAX
UNIT
MIN
MAX
MIN
MAX
f_SCL
I1
t_w(SCLH)
I2
t_w(SCLL)
I3
t_{su(SDAV-SCLH)}
I4
t_{h(SCLH–SDAV)}
Clock frequency, i2cX_scl
Pulse duration, i2cX_scl high
Pulse duration, i2cX_scl low
Setup time, i2cX_sda valid before i2cX_scl
active level
Hold time, i2cX_sda valid after i2cX_scl active
level
60 ⁽³⁾
160 ⁽³⁾
10
0 ⁽²⁾
3.4
1.7
MHz
120 ⁽³⁾
μs
320 ⁽³⁾
μs
10
ns
70
0 ⁽²⁾
150
μs
I5
t_{su(SDAL-SCLH)}
Setup time, i2cX_scl high after i2cX_sda low
160
(for a START⁽⁴⁾ condition or a repeated START
condition)
160
μs
I6
t_{h(SCLH–SDAH)}
Hold time, i2cX_sda low level after i2cX_scl high 160
level (STOP condition)
160
μs
I7
t_{h(SCLH–RSTART)}
Hold time, i2cX_sda low level after i2cX_scl high 160
level (for a repeated START condition)
160
ns
t_R(SCL)
t_R(SCL)
Rise time, i2cX_scl
Rise time, i2cX_scl after a repeated START
condition and after a bit acknowledge
40
80
ns
80
160
ns
t_F(SCL)
t_R(SDA)
t_F(SDA)
C_B
Fall time, i2cX_scl
Rise time, i2cX_sda
Fall time, i2cX_sda
Capacitive load for each bus line
40
80
ns
80
160
ns
80
160
ns
60 ⁽⁵⁾
pF
(1) In i2cX, X is equal to 1, 2, 3, or 4. Note that I2C4 is master transmitter only.
(2) The device provides (via the I²C bus) a hold time of at least 300 ns for the i2cx_sda signal (see the fall and rise time of i2cx_scl) to
bridge the undefined region of the falling edge of i2cx_scl.
(3) HS-mode master devices generate a serial clock signal with a high to low ratio of 1 to 2. t_w(SCLL) > 2 × t_w(SCLH).
(4) After this time, the first clock is generated.
(5) Maximum reference load for i2c4_scl and i2c4_sda is C_B = 15 pF.
i2cX_sda
i2cX_scl
START REPEAT
I5
I6
I1
I2
I3
I4
Figure 6-54. I²C – High-Speed Mode(1) (2) (3)
(1) HS-mode master devices generate a serial clock signal with a high-to-low ratio of 1 to 2. t_w(SCLL) > 2 x t_w(SCLH).
(2) In i2cX, X is equal to 1, 2, 3, or 4. Note that I2C4 is master transmitter only.
(3) After this time, the first clock is generated.
STOP
I7
030-094
Table 6-109. Correspondence Standard vs. TI Timing References
TI-OMAP
STANDARD-I²C
S/F Mode
HS Mode
f_SCL
F_SCL
F_SCLH
I1
t_w(SCLH)
T_HIGH
T_HIGH
I2
t_w(SCLL)
T_LOW
T_LOW
I3
t_{su(SDAV-SCLH)}
T_SU;DAT
T_SU;DAT
I4
t_h(SCLH-SDAV)
T_SU;DAT
T_SU;DAT
I5
t_{su(SDAL-SCLH)}
T_SU;STA
T_SU;STA
I6
t_h(SCLH-SDAH)
T_HD;STA
T_HD;STA
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TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 229
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