OMAP3503DCBBA Datasheet, PDF (210/264 Pages) Texas Instruments – OMAP3515 and OMAP3503 Applications Processors

OMAP3515, OMAP3503
SPRS505H – FEBRUARY 2008 – REVISED OCTOBER 2013
www.ti.com
6.6.2 Multichannel Serial Port Interface (McSPI) Timing
The multichannel SPI is a master/slave synchronous serial bus. The McSPI1 module supports up to four
peripherals and the others (McSPI2, McSPI3, and McSPI4) support up to two peripherals. The following
timings are applicable to the different configurations of McSPI in master/slave mode for any McSPI and
any channel (n).
6.6.2.1 McSPI in Slave Mode
Table 6-71 and Table 6-72 assume testing over the recommended operating conditions (see Figure 6-41).
Table 6-71. McSPI Interface Timing Requirements – Slave Mode^{(1) (2)}
NO.
PARAMETER
1.15 V
MIN
MAX
1/SS 1/t_c(CLK)
0
SS1
SS2
t_j(CLK)
t_w(CLK)
t_{su(SIMOV-CLKAE)}
Frequency, mcspix_clk
Cycle jitter⁽³⁾, mcspix_clk
Pulse duration, mcspix_clk high or low
Setup time, mcspix_simo valid before mcspix_clk
active edge
24
-200
200
0.45*P⁽⁴⁾ 0.55*P⁽⁴⁾
4.2
SS3 t_{h(SIMOV-CLKAE)}
Hold time, mcspix_simo valid after mcspix_clk active
4.6
edge
SS4 t_{su(CS0V-CLKFE)}
Setup time, mcspix_cs0 valid before mcspix_clk first 13.8
edge
SS5 t_{h(CS0I-CLKLE)}
Hold time, mcspix_cs0 invalid after mcspix_clk last
13.8
edge
(1) The input timing requirements are given by considering a rise time and a fall time of 4 ns.
(2) In mcspix, x is equal to 1, 2, 3, or 4.
(3) Maximum cycle jitter supported by mcspix_clk input clock.
(4) P = mcspix_clk clock period
1.0 V
MIN
MAX
12
-200
0.45*P ⁽⁴⁾
9.5
200
0.55*P ⁽⁴⁾
9.9
28.6
28.6
UNIT
MHz
ps
ns
ns
ns
ns
ns
Table 6-72. McSPI Interface Switching Requirements^{(1) (2) (3) (4)}
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
SS6 t_{d(CLKAE-SOMIV)} Delay time, mcspix_clk active edge to mcspix_somi
1.8
15.9
3.2
31.7
ns
shifted
SS7 t_{d(CS0AE-SOMIV)} Delay time, mcspix_cs0 active edge to Modes 0 and 2
mcspix_somi shifted
15.9
31.7
ns
(1) The capacitive load is equivalent to 20 pF.
(2) In mcspix, x is equal to 1, 2, 3, or 4.
(3) The polarity of mcspix_clk and the active edge (rising or falling) on which mcspix_simo is driven and mcspix_somi is latched is all
software configurable.
(4) This timing applies to all configurations regardless of mcspix_clk polarity and which clock edges are used to drive output data and
capture input data.
210 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS
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