OMAP3503DCBBA Datasheet, PDF (207/264 Pages) Texas Instruments – OMAP3515 and OMAP3503 Applications Processors

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OMAP3515, OMAP3503
SPRS505H – FEBRUARY 2008 – REVISED OCTOBER 2013
Table 6-61. McBSP3 (Set #1), 4 (Set #2), and 5 Switching Requirements – Falling Edge and Receive
Mode ⁽¹⁾
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
B2 t_{d(CLKXAE-FSXV)} Delay time, mcbspx_clkx active edge to mcbspx_fsx
0.7
22.2
0.7
44.4
ns
valid
(1) In mcbspx, x identifies the McBSP number: 3, 4, or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode
by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are
specified in the table above. For the McBSP4, these timings concern only Set #2 (multiplexing mode on GPMC pins).
mcbspx_clkr
mcbspx_fsr
mcbspx_dr
B2
B2
B3
B4
D7
D6
Figure 6-37. McBSP Falling Edge Receive Timing in Master Mode
D5
030-072
mcbspx_clkr
mcbspx_fsr
mcbspx_dr
B5
B6
B3
B4
D7
D6
Figure 6-38. McBSP Falling Edge Receive Timing in Slave Mode
D5
030-073
6.6.1.1.4 Transmit Timing with Falling Edge as Activation Edge
Table 6-62 through Table 6-67 assume testing over the recommended operating conditions (see Figure 6-
39 and Figure 6-40).
Table 6-62. McBSP1, 2, and 3 (Sets #2 and #3) Timing Requirements – Falling Edge and Transmit Mode⁽¹⁾
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
B5 t_{su(FSXV-CLKXAE)}
Setup time, mcbspx_fsx valid before mcbspx_clkx
3.7
7.9
ns
active edge
B6 t_{h(CLKXAE-FSXV)}
Hold time, mcbspx_fsx valid after mcbspx_clkx
0.5
0.5
ns
active edge
(1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode
on UART pins) and Set #3 (multiplexing mode on McBSP1 pins).
Table 6-63. McBSP1, 2, and 3 (Sets #2 and #3) Switching Characteristics – Falling Edge and Transmit
Mode ⁽¹⁾
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
B2
t_{d(CLKXAE-FSXV)}
Delay time, mcbspx_clkx active edge to mcbspx_fsx
0.7
14.8
0.7
29.6
ns
valid
B8
t_{d(CLKXAE-DXV)}
Delay time, mcbspx_clkx active edge to Master
mcbspx_dx valid
Slave
0.6
14.8
0.6
29.6
ns
0.6
14.8
0.6
29.6
ns
(1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode
on UART pins) and Set #3 (multiplexing mode on McBSP1 pins).
Copyright © 2008–2013, Texas Instruments Incorporated
TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 207
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