IC-MB4_15 Datasheet, PDF (29/40 Pages) IC-Haus GmbH – BiSS INTERFACE MASTER

iC-MB4
BiSS INTERFACE MASTER
MAFS
0
1
Addr. 0xF5; bit 4
R/W
Controlling selected(CHSEL) MA clock line: using
MA signal
Controlling selected(CHSEL) MA clock line: using
MAVS level
Table 40: Selected MA line control selection
MAVS
0
1
Addr. 0xF5; bit 5
R/W
Low definition of selected(CHSEL) MA clock lines
High definition of selected(CHSEL) MA clock lines
Table 41: Selected MA line control level
preliminary
Rev B2, Page 29/40
MAFO
0
1
Addr. 0xF5; bit 6
R/W
Controlling unselected(CHSEL) MA clock line: using
MA signal
Controlling unselected(CHSEL) MA clock line: using
MAVS level
Table 42: Not selected MA line control selection
MAVO
0
1
Addr. 0xF5; bit 7
R/W
Low definition of unselected(CHSEL) MA clock lines
High definition of unselected(CHSEL) MA clock lines
Table 43: Not selected MA line control level
CONFIGURATION MASTER
Master Clock MA
The master clock, either generated by the basic clock
of the internal 20 MHz oscillator (CLKENI = 1) or by an
external clock oscillator (CLKENI = 0) which supplies
pin CLK, is set with the aid of the frequency division
register FREQ (address 0xE6).
The MA clock frequency for both BiSS and SSI modes
is set via FREQ(4:0) in accordance with table 44. With
an external clock pulse of f(CLK) = 20 MHz clock fre-
quencies ranging from 62.5 kHz to 10 MHz can thus be
selected for sensor data transmission.
FREQS
0x00
0x01
0x02
0x03
...
0x09
...
0x0D
0x0E
0x0F
Addr. 0xE6; bit 4:0
f_CLK/ 2
f_CLK/ 4
f_CLK/ 6
f_CLK/ 8
...
f_CLK/ 20
...
f_CLK/ 28
f_CLK/ 30
f_CLK/ 32
R/W
0x10
0x11
0x12
0x13
...
0x1D
0x1E
0x1F
”not permitted”
f_CLK/ 40
f_CLK/ 60
f_CLK/ 80
...
f_CLK/ 280
f_CLK/ 300
f_CLK/ 320
Table 44: Sensor data clock frequency
Both BiSS and SSI devices recognize an idle bus at
the end of a transmission cycle via a monoflop timeout
elapsing (timeoutSENS, see BiSS protocol). The choice
of possible clock frequencies is thus limited as the du-
ration of both the high and low level may not exceed
the shortest timeout of all of the connected subscribers
(slaves).
BiSS B devices switch to register mode when recogniz-
ing that the bus is idle after a high-low transition at the
clock input and signal this state back to the master on
the data line.
The clock frequency in BiSS B register mode is set via
parameter FREQ and within a range of 244 Hz to 5 MHz.
The selection is also limited as a different monoflop
timeout does now recognize the idle bus at the end of
the cycle (timeoutREG, see BiSS B protocol).
FREQR
Addr. 0xE6; bit 7:5
R/W
0..
FreqSens/ (2 * (FREQ(7:5)+1) )
7
0
FreqSens / 2
1
FreqSens / 4
2
FreqSens / 8
3
FreqSens / 16
4
FreqSens / 32
5
FreqSens / 64
6
FreqSens / 128
7
FreqSens / 256
Table 45: BiSS B register data frequency
BiSS B devices typically require a minimum clock fre-
quency (such as 250 kHz) due to the MA clock form
has to be evaluated as a possible PWM signal for regis-
ter communication. BiSS C devices generally permit a
lower clock frequency. BiSS C devices do not use the
MA clock duty cycle (PWM signal) and can be operated
down to 80 kHz. SSI devices generally permit a lower
clock frequency and with extended SSI the register ac-