IC-MB4_15 Datasheet, PDF (24/40 Pages) IC-Haus GmbH – BiSS INTERFACE MASTER

iC-MB4
BiSS INTERFACE MASTER
SENSOR DATA
preliminary
Rev B2, Page 24/40
The transmission of sensor data begins when the mas-
ter outputs the clock signal at pin MA1 with the clock
frequency selected by FREQ. The line delay, i.e. the
transmission propagation until an acknowledgement
is generated at SL1, is determined from the second
falling edge onwards. While the clock continues to be
output at MA1, the master waits for the slaves start bit
(1) signaling the start of data transmission. Afterwards
this the actual clocking out of sensor data begins, i.e.
the sensors place a new bit on the SL1 line with each
rising edge on the MA1 line.
The sensor data being input into the master and the
subsequent sets of CRC data are written to the ap-
propriate sensor data RAM. At the same time the new
CRC value is calculated in accordance with the CRC
polynomial stored in the configuration RAM. Should the
system ascertain after entry of the last CRC bit, that
transmission was faulty, the relevant validity message
is deleted and error message nSENSERR set in the
status register. At the same time the sensor data RAM
banks are swapped.
SCDATA
Addr. 0x00 . . . 0x3F; bit
R/W
7:0
0x00
SCDATA1(7:0)
0x01
SCDATA1(15:8)
0x02
SCDATA1(23:16)
0x03
SCDATA1(31:24)
0x04
SCDATA1(39:32)
0x05
SCDATA1(47:40)
0x06
SCDATA1(55:48)
0x07
SCDATA1(63:56)
0x08 . .
0x0F
SCDATA2(63:0)
0x10 . .
0x17
SCDATA3(63:0)
0x18 . .
0x1F
SCDATA4(63:0)
0x20 . .
0x27
SCDATA5(63:0)
0x28 . .
0x2F
SCDATA6(63:0)
0x30 . .
0x37
SCDATA7(63:0)
0x38 . .
0x3F
SCDATA8(63:0)
Table 14: Address mapping of sensor data
In order for new sensor data to be read in during con-
troller accesses, iC-MB4 has dual memory banks for
sensor data. While sensor data is being read and writ-
ten into the first RAM bank, the second RAM bank
section with the prior read sensor data can be read out
by the controller. The relevant sensor data memory
banks are swapped at the end of the reading procedure.
This can be prevented by the controller entering the
command register bit HOLDBANK. Simultaneously the
status information 1 (validity register in address 0xF1
. . . 0xF2) and status information 2 (CDS2 and CDS1 in
address 0xF8) are also swapped.
Arrangement of Sensor Data in the RAM
The sensor data memory bank has 8 bytes of mem-
ory for each slave which can be interpreted as 64 bits
of memory in the array 0bxxxx.x111 to 0bxxxx.x000.
The sensor data is written to memory area [SDLEN
- 1:0] with SDLEN marking the length of the relevant
data. If there is space in the available memory for the
processed CRC bits and NOCRC = 0, the read CRC
bits are stored with the above data at positions [63:63 -
(CRCLEN-1)].