IC-MB4_15 Datasheet, PDF (16/40 Pages) IC-Haus GmbH – BiSS INTERFACE MASTER

iC-MB4
BiSS INTERFACE MASTER
preliminary
Rev B2, Page 16/40
OPERATING REQUIREMENTS: BiSS Interface (SSI mode)
Operating conditions: register bit SELSSI = 1; VDD = 3. . . 5.5 V, Tj = -40. . . 125 °C
Alias: MA = MA1/MA2_NMA1, SL = SL1/SL2_NSL1
Item Symbol Parameter
No.
Conditions
I501 TMAS Clock Period
FreqSens via FREQ(4:0) selected in
accordance with table 45 on page 29
I502 tMASh Clock Signal Hi Level Duration
I503 tMASl
Clock Signal Lo Level Duration
I504 tsDC
I505 thDC
Setup Time: SL stable before MA lo→hi
Hold Time: SL stable after MA lo→hi
Min.
2
50
50
30
0
Max.
320
Unit
1/f(CLK)
50
%
TMAS
50
%
TMAS
ns
ns
Figure 10: Timing diagram SSI mode
SLx line sampling
In SSI interface mode SL1 values are sampled with the rising edge at MA1. An overall delay of the sensor
response to the clock at MA1, caused by process times in the sensor or transmission times, is permissible up to
the length of one clock cycle.