IC-MB4_15 Datasheet, PDF (11/40 Pages) IC-Haus GmbH – BiSS INTERFACE MASTER

iC-MB4
BiSS INTERFACE MASTER
preliminary
Rev B2, Page 11/40
OPERATING REQUIREMENTS: µC Interface, INTEL mode
Operating conditions: CFGSPI = 0, INT_NMOT = 1, VDD = 3.0 . . . 5.5 V, Tj = -40 . . . 125 °C
lo input level = 0 . . . 0.8 V, hi input level = 2.0 V . . . VDD, lo output level = 0 . . . 0.4 V, hi output level = 2.4 V . . . VDD
Alias: NRD = NRD_RNW, NWR = NWR_E
Item Symbol Parameter
No.
Conditions
Min.
I001 tsCA
Setup Time:
10
NCS lo before ALE hi→lo
I002 tsDA
Setup Time:
15
Data stable before ALE hi→lo
I003 thDA
Hold Time:
15
Data stable after ALE hi→lo
I004 tAh
Signal Duration:
10
ALE at high level
I005 tsAR
Setup Time:
10
ALE lo before NRD hi→lo
I006 thAR
Hold Time:
NCS = lo
10
ALE lo after NRD lo→hi
I007 tRl
Signal Duration:
NCS = lo
10
NRD at low level
I008 tpRD1
Propagation Delay:
Data stable after NRD hi→lo
NCS = lo, CL = 50 pF
I009 tpRD2
Propagation Delay:
Data bus high impedance after NRD
lo→hi
NCS = lo, CL = 50 pF
I010 thCR
Hold Time:
10
NCS lo after NRD lo→hi
I011 tsAW
Setup Time:
10
ALE lo before NWR hi→lo
I012 thAW
Hold Time:
NCS = lo
10
ALE lo after NWR lo→hi
I013 tWl
Signal Duration:
NCS = lo
10
NWR at low level
I014 tsDW
Setup Time:
NCS = lo
15
Data stable before NWR lo→hi
I015 thDW
Hold Time:
NCS = lo
15
Data stable after NWR lo→hi
I016 thCW
Hold Time:
10
NCS lo after NWR lo→hi
Unit
Max.
ns
ns
ns
ns
ns
ns
ns
25
ns
25
ns
ns
ns
ns
ns
ns
ns
ns
Figure 3: Read cycle (Intel mode)
Figure 4: Write cycle (Intel mode)