Z86D86 Datasheet, PDF (75/80 Pages) Zilog, Inc. – 28-Pin Low-Voltage OTP Microcontroller

Z86D86
28-Pin Low-Voltage OTP Microcontroller
67
WDTMR During STOP (D3)
This bit determines whether or not the WDT is active during STOP Mode. Since
the XTAL clock is stopped during STOP Mode, the on-board RC has to be
selected as the clock source to the WDT/POR counter. A 1 indicates active during
STOP. The default is 1.
Clock Source for WDT (D4)
This bit determines which oscillator source is used to clock the internal POR and
WDT counter chain. If the bit is a 1, the internal RC oscillator is bypassed, and the
POR and WDT clock source is driven from the external pin, XTAL1. The default
configuration of this bit is 0, which selects the RC oscillator. See Figure 51.
5 Clock
Filter
*CLR2 _{18 Clock Reset Reset}
CLK
Generator
Ck source
Select
(WDTMR)
XTAL
V_DD
VBO/VLV
2V Ref.
WDT
WDT TAP SELECT
M
POR 5 ms 10 ms 20 ms 80 ms
CLK ^{256 TpC 512 TpC 1024 TpC} 4096 TpC
Internal
RD OSC.
U
X
*CLR1 WDT/POR Counter Chain
Low Operating
+ ^{Voltage Det.}
–
V_CC
12 ns Glitch Filter
From Stop Mode
Recovery Source
Stop Delay
Select (SMR)
*CLR1 and CLR2 enable the WDT/POR and
18 Clock Reset timers upon a Low-to-High input translation.
Internal
Reset
Active
High
Figure 51. Resets and WDT
PS008905-0105
PRELIMINARY