Z86D86 Datasheet, PDF (72/80 Pages) Zilog, Inc. – 28-Pin Low-Voltage OTP Microcontroller

Z86D86
28-Pin Low-Voltage OTP Microcontroller
64
Stop-Mode Recovery Register 2 (SMR2)
This register determines the mode of Stop-Mode Recovery for SMR2 (see
Figure 50).
SMR2 (0F) DH
D7 D6 D5 D4 D3 D2 D1 D0
Reserved (must be 0)
Reserved (must be 0)
Stop-Mode Recovery Source 2
000 = POR Only *
001 = NAND P20, P21, P22, P23
010 = NAND P20, P21, P22, P33, P24, P25, P26, P27
011 = NOR P31, P32, P33
100 = NAND P31, P32, P33
101 = NOR P31, P32, P33, P00, P07
110 = NAND P31, P32, P33, P00, P07
111 = NAND P31, P32, P33, P20, P21, P22
* Default setting after reset
** At the XOR gate input
Reserved (must be 0)
Recovery Level **
0 = Low *
1 = High
Reserved (must be 0)
Note: If used in conjunction with SMR,
either of the two specified events
causes a Stop-Mode Recovery.
Figure 50. Stop-Mode Recovery Register 2—(0F) DH:D2–D4, D6 Write Only
If SMR2 is used in conjunction with SMR, either of the specified events causes a
Stop-Mode Recovery.
Note: Port pins configured as outputs are ignored as a SMR or SMR2
recovery source. For example, if the NAND or P23–P20 is
selected as the recovery source and P20 is configured as an
output, the remaining SMR pins (P23–P21) form the NAND
equation.
Table 24 describes the contents of the Stop-Mode Recovery register 2.
PS008905-0105
PRELIMINARY