Z53C80 Datasheet, PDF (31/40 Pages) Zilog, Inc. – SMALL COMPUTER SYSTEM INTERFACE (SCSI)

ZILOG
AC CHARACTERISTICS
DMA Write Target Send Cycle Table
No
Description
1
DRQ Low from /DACK Low
2
/DACK High to DRQ High
3
Write Enable Width ^[1]
4
/DACK Hold from /WR High
5
Data Setup to End of Write Enable ^[1]
6
Data Hold Time from End of /WR
7
Width of /EOP Pulse ^[2]
8
/ACK Low to /REQ High
9
/REQ from End of /DACK (/ACK High)
10
/ACK Low to DRQ High (Target)
11
/ACK High to /REQ Low (/DACK High)
12
Data Hold from Write Enable
13
Data Setup to /REQ Low (Target)
Notes:
[1] Write Enable is the occurrence of /IOW and /DACK
[2] /EOP, /WR, and /DACK must be concurrently Low for at least T7 for
proper recognition of the /EOP pulse.
Z53C80 SCSI
Min
Max
60
30
50
0
50
25
50
80
90
70
100
15
55
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PS97SCC0200
31