Z53C80 Datasheet, PDF (10/40 Pages) Zilog, Inc. – SMALL COMPUTER SYSTEM INTERFACE (SCSI)

ZILOG
FUNCTIONAL DESCRIPTION (Continued)
Z53C80 SCSI
Bit 0. Arbitrate. The Arbitrate bit is set (1) to start the
Arbitration process. Prior to setting this bit, the Output Data
Register should contain the proper SCSI device ID value.
Only one data bit should be active for SCSI Bus Arbitration.
The SCSI waits for a Bus-Free condition before entering
the Arbitration phase. The results of the Arbitration phase
is determined by reading the status bits LA and AIP
(Initiator Command Register, bits 5 and 6, respectively).
Bit 1. DMA Mode. The DMA Mode bit is normally used to
enable a DMA transfer and must be set (1) prior to writing
Start DMA Send Register, Start DMA Target Receive
Register, and Start DMA Initiator Receiver Register. These
three registers are used to start DMA transfers. The Target
Mode bit (Mode Register, bit 6) must be consistent with
writes to Start DMA Target Receive and Start DMA Initiator
Receive Registers [i.e., set (1) for a write to start DMA
Target Receive Register and set (0) for a write to Start DMA
Initiator Receive Register]. The control bit Assert Data Bus
(Initiator Command Register, bit 0) must be True (1) for all
DMA send operations. In the DMA mode, /REQ and /ACK
are automatically controlled.
The DMA Mode bit is not reset upon the receipt of an /EOP
signal. Any DMA transfer is stopped by writing a zero into
this bit location; however, care must be taken not to cause
/CS and /DACK to be active simultaneously.
Bit 2. Monitor Busy. The Monitor Busy bit, when True (1),
causes an interrupt to be generated for an unexpected
loss of /BSY. When the interrupt is generated due to loss of
/BSY, the lower six bits of the Initiator Command Register
are reset (0) and all signals are removed from the SCSI
Bus.
Bit 3. Enable/EOP interrupt. The enable /EOP interrupt,
when set (1), causes an interrupt to occur when the /EOP
(End of Process) signal is received from the DMA controller
logic.
Bit 4. Enable Parity Interrupt. The Enable Parity Interrupt
bit, when set (1), will cause an interrupt (IRQ) to occur if a
parity error is detected. A parity interrupt will only be
generated if the Enable Parity Checking bit (bit 5) is also
enabled (1).
Bit 6. Targetmode. The Targetmode bit allows the SCSI to
operate as either a SCSI Bus Initiator, bit reset (0), or as a
SCSI Bus Target device, bit set (1). If the signals /ATN and
/ACK are to be asserted on the SCSI Bus, the Targetmode
bit must be reset (0). If the signals C//D, I//O, /MSG, and
/REQ are to be asserted on the SCSI Bus, the Targetmode
bit must be set (1).
Bit 7. 0. Bit 7 should be written with a zero for proper
operation.
Target Command Register. Address 3 (Read/Write). When
connected as a target device, the Target Command
Register (Figure 11) allows the CPU to control the SCSI Bus
Information Transfer phase and/or to assert /REQ by writing
this register. The Targetmode bit (Mode Register, bit 6)
must be True (1) for bus assertion to occur. The SCSI Bus
phases are described in Table 2.
Table 2. SCSI Information Transfer Phase
Bus Phase
ASSERT ASSERT ASSERT
I//O
C//D
/MS
Data Out
Unspecified
Command
0
0
0
0
0
1
0
1
0
Message Out
0
1
1
Data In
1
0
0
Unspecified
1
0
1
Status
Message In
1
1
0
1
1
1
When connected as an Initiator with DMA Mode True, if the
phase lines I//O, C//D, and /MSG do not match the phase
bits in the Target Command Register, a phase mismatch
interrupt is generated when /REQ goes active. To send
data as an Initiator, the Assert I//O, Assert C//D, and Assert
/MSG bits must match the corresponding bits in the Current
SCSI Bus Status Register. The Assert /REQ bit (bit 3) has
no meaning when operating as an Initiator.
Bits 4, 5, and 6 are not used.
Bit 5. Enable Parity Checking. The Enable Parity Checking
bit determines whether parity errors are ignored or saved
in the parity error latch. If this bit is reset (0), parity is
ignored. Conversely, if this bit is set (1), parity errors are
saved.
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PS97SCC0200