Z53C80 Datasheet, PDF (13/40 Pages) Zilog, Inc. – SMALL COMPUTER SYSTEM INTERFACE (SCSI)

ZILOG
Start DMA Initiator Receive. Address 7 (Write Only). This
register is written to initiate a DMA receive from the SCSI
Bus to the DMA, for Initiator operation only. The DMA Mode
bit (bit 6) must be False (0) in the Mode Register prior to
writing this register.
Reset Parity/Interrupt. Address 7 (Read Only). Reading
this register resets the Parity Error bit (bit 5), the Interrupt
Request bit (bit 4), and the Busy Error bit (bit 2) in the Bus
and Status Register.
On-Chip SCSI Hardware Support. The SCSI is easy to
use because of its simple architecture. The chip allows
direct control and monitoring of the SCSI Bus by providing
a latch for each signal. However, portions of the protocol
define timings which are much too quick for traditional
microprocessors to control. Therefore, hardware support
has been provided for DMA transfers, bus arbitration,
phase change monitoring, bus disconnection, bus reset,
parity generation, parity checking, and device selection/
reselection.
Arbitration is accomplished using a Bus-Free filter to
continuously monitor /BSY. If /BSY remains inactive for at
least 400 ns, the SCSI is considered free and Arbitration
may begin. Arbitration will begin if the bus is free, /SEL is
inactive, and the Arbitrate bit (Mode Register, bit 0) is
active. Once arbitration has begun (/BSY asserted), an
arbitration delay of 2.2 µs must elapse before the Data Bus
can be examined to determine if Arbitration is enabled.
This delay is implemented in the controlling software
driver.
The Z53C80 is a clockwise device. Delays such as bus-
free delay, bus-set delay, and bus-settle delay are
implemented using gate delays. These delays may differ
between devices because of inherent process variations,
but are well within the proposed ANSI X3.131 - 1986
specification.
Interrupts. The Z53C80 provides an interrupt output (IRQ)
to indicate a task completion or an abnormal bus
occurrence. The use of interrupts is optional and may be
disabled by resetting the appropriate bits in the Mode
Register or the Select Enable Register.
When an interrupt occurs, the Bus and Status Register and
the Current SCSI Bus Status Register (Figures 12 and 14)
must be read to determine which condition created the
interrupt. IRQ can be reset simply by reading the Reset
Parity/Interrupt Register or by an external chip reset
/RESET active for 100 ns.
Z53C80 SCSI
Assuming the Z53C80 has been properly initialized, an
interrupt will be generated if the chip is selected or
reselected, if an /EOP signal occurs, if a parity error occurs
during a data transfer, if a bus phase mismatch occurs, or
if a SCSI Bus disconnection occurs.
Selection Reselection. The Z53C80 generates a select
interrupt if SEL is active (0), its device ID is True and /BSY
is False for at least a bus-settle delay. If I//O is active, this
is considered a reselect interrupt. The correct ID bit is
determined by a match in the Select Enable Register. Only
a single bit match is required to generate an interrupt. This
interrupt may be disabled by writing zeros into all bits of the
Select Enable Register.
If parity is supported, parity should be good during the
selection phase. Therefore, if the Enable Parity bit (Mode
Register, bit 5) is active, the Parity Error bit is checked to
ensure that a proper selection has occurred. The Enable
Parity Interrupt bit need not be set for this interrupt to be
generated.
The proposed SCSI specification also requires that no
more than two device IDs be active during the selection
process. To ensure this, the Current SCSI Data Register is
read.
The proper values for the Bus and Status Register and the
Current SCSI Bus Status Register are displayed in Figures
15 and 16, respectively.
D7
D0
0 0 0 1X 0X 0
/ACK
/ATN
Busy Error
Phase Match
Interrupt Request Active
Parity Error
DMA Request
End of DMA
Figure 15. Bus and Status Register
PS97SCC0200
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