Z53C80 Datasheet, PDF (25/40 Pages) Zilog, Inc. – SMALL COMPUTER SYSTEM INTERFACE (SCSI)

ZILOG
AC CHARACTERISTICS
CPU Read Cycle Timing Diagram
A2-A0
/SCSICS
/RD
D7-D0
1
2
3
4
5
Z53C80 SCSI
Figure 46. CPU Read Cycle
AC CHARACTERISTICS
CPU Read Cycle Table
No
Description
1
Address Setup to Read Enable ^[1]
2
Address Hold from End Read Enable ^[1]
3
Chip Select Hold from End of /RD
4
Data Access Time from Read Enable ^[1]
5
Data Hold Time from End of Read Enable ^[1]
Note:
[1] Read Enable is the occurrence of /RD and /CS.
Min
Max
10
10
0
70
10
Units
ns
ns
ns
ns
ns
PS97SCC0200
25