Z53C80 Datasheet, PDF (16/40 Pages) Zilog, Inc. – SMALL COMPUTER SYSTEM INTERFACE (SCSI)

ZILOG
Z53C80 SCSI
FUNCTIONAL DESCRIPTION (Continued)
A phase mismatch prevents the recognition of /REQ and
removes the chip from the bus during an Initiator send
operation (/DB7-/DB0 and /DBP will not be driven even
through the Assert Data Bus bit (Initiator Command Register,
bit 0). This may be disabled by resetting the DMA Mode bit
(Note: It is possible for this interrupt to occur when
connected as a Target if another device is driving the
phase lines to a different state).
The proper values for the Bus and Status Register and the
Current SCSI Bus Status Register are displayed in Figures
23 and 24, respectively.
D7
D0
0 0 0 1 0 0X 0
/ACK
/ATN
Busy Error
Phase Match
Interrupt Request Active
Parity Error
DMA Request
End of DMA
Loss of BSY. If the Monitor Busy bit (bit 2) in the Mode
Register is active, an interrupt is generated if the BSY
signal goes FALSE for at least a bus-settle delay. This
interrupt is disabled by resetting the Monitor Busy bit.
Register values are displayed in Figures 25 and 26.
D7
D0
0 00 1X10 0
/ACK
/ATN
Busy Error
Phase Match
Interrupt Request Active
Parity Error
DMA Request
End of DMA
Figure 25. Bus and Status Register
D7
D0
0 0 0 XX X 0 0
Figure 23. Bus and Status Register
D7
D0
0 1XXXX 0X
/DBP
/SEL
I//O
C//D
/MSQ
/REQ
/BSY
/RST
/DBP
/SEL
I//O
C//D
/MSQ
/REQ
/BSY
/RST
Figure 26. Current SCSI Bus Status Register
Figure 24. Current SCSI Bus Status Register
16
PS97SCC0200