Z86C02 Datasheet, PDF (24/37 Pages) Zilog, Inc. – Two On-Board Comparators

Z86C02/E02/L02
Cost Effective, 512-Byte ROM CMOS Z8^® Microcontrollers
Zilog
FUNCTIONAL DESCRIPTION (Continued)
HALT Mode. This instruction turns off the internal CPU
clock but not the crystal oscillation. The counter/timer and
external interrupts IRQ0, IRQ1, IRQ2 and IRQ3 remain ac-
tive. The device is recovered by interrupts, either external-
ly or internally generated. An interrupt request must be ex-
ecuted (enabled) to exit HALT mode. After the interrupt
service routine, the program continues from the instruction
after the HALT.
STOP Mode. This instruction turns off the internal clock
and external crystal oscillation and reduces the standby
current to 10 µA. The STOP mode is released by a RESET
through a Stop-Mode Recovery (pin P27). A Low input
condition on P27 releases the STOP mode. Program exe-
cution begins at location 000C(Hex). However, when P27
is used to release the STOP mode, the I/O port mode reg-
isters are not reconfigured to their default power-on condi-
tions. This prevents any I/O, configured as output when the
STOP instruction was executed, from glitching to an un-
known state. To use the P27 release approach with STOP
mode, use the following instruction:
LD
P2M, #1XXX XXXXB
NOP
STOP
Notes:
X = Dependent on user’s application.
Stop-Mode Recovery pin P27 is not edge triggered.
In order to enter STOP or HALT mode, it is necessary to
first flush the instruction pipeline to avoid suspending exe-
cution in mid-instruction. To do this, the user executes a
NOP (opcode=FFH) immediately before the appropriate
SLEEP instruction, i.e.:
Watch-Dog Timer (WDT). The Watch-Dog Timer is en-
abled by instruction WDT. When the WDT is enabled, it
cannot be stopped by the instruction. With the WDT in-
struction, the WDT is refreshed when it is enabled within
every 1 Twdt period; otherwise, the controller resets itself,
The WDT instruction affects the flags accordingly; Z=1,
S=0, V=0. WDT = 5F (Hex)
Opcode WDT (5FH). The first time opcode 5FH is execut-
ed, the WDT is enabled and subsequent execution clears
the WDT counter. This must be done at least every T_WDT;
otherwise, the WDT times out and generates a reset. The
generated reset is the same as a power-on reset of T_POR,
plus 18 XTAL clock cycles.The WDT does not run in stop
mode, unless the permanent WDT enable option is select-
ed. The WDT does not run in halt mode unless WDH in-
struction is executed or permanent WDT enable option is
selected.
Opcode WDH (4FH). When this instruction is executed it
enables the WDT during HALT. If not, the WDT stops
when entering HALT. This instruction does not clear the
counters, it just makes it possible to have the WDT running
during HALT mode. A WDH instruction executed without
executing WDT (5FH) has no effect.
Note: Opcode WDH and permanently enabled WDT is
not directly supported by the Z86CCP00ZEM.
Auto Reset Voltage (V_LV). The Z8 has an auto-reset built-
in. The auto-reset circuit resets the Z8 when it detects the
V_CC below V_LV. Figure 18 shows the Auto Reset Voltage
versus temperature.
FF NOP
6F
STOP
or
FF NOP
7F
HALT
; clear the pipeline
; enter STOP mode
; clear the pipeline
; enter HALT mode
24
PRELIMINARY
DS96DZ80301