Z86C02 Datasheet, PDF (19/37 Pages) Zilog, Inc. – Two On-Board Comparators

Zilog
Z86C02/E02/L02
Cost Effective, 512-Byte ROM CMOS Z8^® Microcontrollers
FUNCTIONAL DESCRIPTION
The following special functions have been incorporated RESET. This function is accomplished by means of a Pow-
1 ^{into the Z86C02/E02/L02 devices to enhance the standard er-On Reset or a Watch-Dog Timer Reset. Upon power-}
Z8 core architecture to provide the user with increased de- up, the Power-On Reset circuit waits for T_POR ms, plus 18
sign flexibility.
clock cycles, then starts program execution at address
000C (Hex) (Figure 11). The control registers' reset value
is shown in Table 4.
POR
(Cold Start)
P27
(Stop Mode)
INT OSC
Delay Line
T_POR ms
XTAL OSC
18 CLK
Reset Filter
Chip
Reset
Figure 11. Internal Reset Configuration
Power-On Reset (POR). A timer circuit clocked by a ded-
icated on-board RC oscillator is used for a POR timer func-
tion. The POR time allows V_CC and the oscillator circuit to
stabilize before instruction execution begins. The POR
timer circuit is a one-shot timer triggered by one of the four
following conditions:
s Power bad to power good status
s Stop-Mode Recovery
s WDT time-out
s WDH time-out (in Halt Mode)
s WDT time-out (in Stop Mode)
Watch-Dog Timer Reset. The WDT is a retriggerable
one-shot timer that resets the Z8 if it reaches its terminal
count. The WDT is initially enabled by executing the WDT
instruction and is retriggered on subsequent execution of
the WDT instruction. The timer circuit is driven by an on-
board RC oscillator. If the permanent WDT option is select-
ed then the WDT is enabled after reset and operates in
RUN Mode, HALT mode, STOP mode and cannot be dis-
abled. If the permanent WDT option is not selected then
the WDT, when enabled by the user's software, does not
operate in STOP Mode, but it can operate in HALT Mode
by using a WDH instruction.
Table 4. Control Register
Reset Condition
Addr Reg. D7 D6 D5 D4 D3 D2 D1 D0 Comments
FF SPL 0 0 0 0 0 0 0 0
FE GPR 0 0 0 0 0 0 0 0
FD RP
00000000
FC FLAGS U U U U U U U U
FB IMR 0 U U U U U U U
FA IRQ
U U 0 0 0 0 0 0 IRQ3 is used
for positive
edge
detection
F9 IPR U U U U U U U U
F8 P01M U U U 0 U U 0 1
F7* P3M U U U U U U 0 0 P2 open-drain
F6* P2M 1 1 1 1 1 1 1 1 Inputs after
reset
F3 PRE1 U U U U U U 0 0
F2 T1
UUUUUUUU
F1 TMR 0 0 0 0 0 0 0 0
Note:
*Registers are not reset after a STOP-Mode Recovery
using P27 pin. A subsequent reset will cause these control
registers to be reconfigured as shown in Table 4 and the
user must avoid bus contention on the port pins or it may
affect device reliability.
DS96DZ80301
PRELIMINARY
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