Z86C02 Datasheet, PDF (22/37 Pages) Zilog, Inc. – Two On-Board Comparators

Z86C02/E02/L02
Cost Effective, 512-Byte ROM CMOS Z8^® Microcontrollers
FUNCTIONAL DESCRIPTION (Continued)
OSC
÷2 ^*
Internal
Clock
External Clock
Clock
Logic
÷4
6-Bit
Down
Counter
8-Bit
Down
Counter
IRQ5
Internal Clock
Gated Clock
Triggered Clock
T_IN P31
PRE1
Initial Value
Register
T1
Initial Value
Register
T1
Current Value
Register
Write
Write
Read
Internal Data Bus
Figure 15. Counter/Timers Block Diagram
Zilog
Interrupts. The Z8 has five interrupts from four different
sources. These interrupts are maskable and prioritized
(Figure 16). The sources are divided as follows: the falling
edge of P31 (AN1), P32 (AN2), P33 (REF), the rising edge
of P32 (AN2), and one counter/timer. The Interrupt Mask
Register globally or individually enables or disables the
five interrupt requests (Table 5).
When more than one interrupt is pending, priorities are re-
solved by a programmable priority encoder that is con-
trolled by the Interrupt Priority register. All Z8 interrupts are
vectored through locations in program memory. When an
Interrupt machine cycle is activated, an Interrupt Request
is granted. This disables all subsequent interrupts, saves
the Program Counter and Status Flags, and then branches
to the program memory vector location reserved for that in-
terrupt. This memory location and the next byte contain the
16-bit starting address of the interrupt service routine for
that particular interrupt request.
To accommodate polled interrupt systems, interrupt inputs
are masked and the interrupt request register is polled to
determine which of the interrupt requests needs service.
User must select any Z86E08 mode in Zilog's C12 ICE-
BOX™ emulator. The rising edge interrupt is not directly
supported on the Z86CCP00ZEM emulator.
Table 5. Interrupt Types, Sources, and Vectors
Name Source
IRQ0 AN2(P32)
Vector
Location
0,1
IRQ1 REF(P33)
2,3
IRQ2 AN1(P31)
4,5
IRQ3 AN2(P32)
6,7
IRQ4 Reserved
8,9
IRQ5 T1
10,11
Notes:
F = Falling edge triggered
R = Rising edge triggered
Comments
External (F)Edge
External (F)Edge
External (F)Edge
External (R)Edge
Reserved
Internal
22
PRELIMINARY
DS96DZ80301